International Business Machines Corporation

Drexel University

Divya Pathak

Ioannis Savidis

Phillip John Restle

Christos Vezyrtzis

Aisha Walcott

Bharath Dandala

Pierce I-Jen Chuang

Ching-Huei Tsou

Piyush Madan

Michal Rosen-Zvi

Ananya Aniruddha Poddar

Pierce I Chuang

Diwakar Mahajan

Houman Homayoun

Parthasarathy Suryanarayanan

Systems, devices, computer-implemented methods, and/or computer program products that facilitate artificial intelligence (AI)-assisted curation of non-pharmaceutical intervention (NPI) data from heterogeneous data sources. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise an extraction component and a change detection component. The extraction component can extract candidate non-pharmaceutical intervention (NPI) events from data associated with a defined disease. The change detection component can evaluate the candidate NPI events for inclusion in a dataset storing NPI events in a defined format.

Artificial intelligence-assisted non-pharmaceutical intervention data curation

The increasing power density and, therefore, current consumption of high performance integrated circuits (ICs) results in increased challenges in the design of a reliable and efficient on-chip power delivery network. In particular, meeting the stringent on-chip impedance of the IC requires circuit and system techniques to mitigate high frequency noise that results due to resonance between the package inductance and the onchip capacitance. In this paper, a novel circuit technique is proposed to suppress high frequency noise through the use of a hyperabrupt junction tuning varactor diode as a decoupling capacitor for noise critical functional blocks. With the proposed circuit technique, the voltage droops and overshoots on the onchip power distribution network are suppressed by up to 60% as compared to MIM or deep trench decoupling capacitors of the same capacitance. In addition, there is no added latency to react to power supply noise and there is no degradation to circuit performance as compared to existing techniques in commercial products and literature.

On-chip power supply noise suppression through hyperabrupt junction varactors

A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.

Work load scheduling for multi core systems with under-provisioned power delivery

A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.

Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors

A circuit that detects the power supply voltage requirement of each voltage domain in an IC includes 1) a ring oscillator in each voltage domain, and 2) a power module. Two different circuit implementations of the power module may provide a precise reference voltage to on-chip voltage regulators (LDO or DC-DC switching buck converter). The power module supports DVFS and can provide the desired power supply voltage for advanced CMOS technology nodes (45 nm and beyond) in less than 100 ns. The voltage detection circuit clamps the voltage to the desired level to address power supply voltage variations due to PVT and ageing. The proposed technique has minimal power and area overhead to compensate for the power supply voltage variation, thus reducing power supply voltage margins which yields higher power saving.

Power supply voltage detection and power delivery circuit

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Philadelphia, PA, United States of America

Divya Pathak