International Business Machines Corporation

Divya Kumudprakash Joshi

Bodo Hoppe

Gerrit Koch

Parminder Singh

Ophir Erez

Richard Frank Rizzolo

Sean Michael Carey

Tuhin Mahmud

Bryan Glen Hickerson

Erica Stuecheli

John Reysa

Paul Jacob Logsdon

Edward J Kaminski

Brian Kozitza

Sreekala Anandavally

Mohamed Baker Alawieh

Kyle Davis

Shaun Thomas Uldrikis

William Rurik

A computer-implemented method, system, and computer program product for testing hardware in an environment involving a checkstop. Errors are injected into a model of a design under test (DUT), which includes a first hardware component interfaced with a second hardware component, at various states causing an occurrence of a checkstop in the first hardware component. A simulation of the model of the DUT is then performed with the injected errors for a number of cycles after the checkstop based on a quiesce time where the injected errors are suppressed. Furthermore, a post-processing script is executed to test a model of the DUT which ignores the errors of the first hardware component that were identified after the checkstop in the simulation of the model of the DUT. Any non-ignored errors from the execution of the post-processing script are detected and analyzed to determine if the second hardware component failed the test.

Continuing to test a hardware component after occurrence of a checkstop

A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests ('LBIST') trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

Error injection for timing margin protection and frequency closure

Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.

Clustering simulation failures for triage and debugging

Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.

Determine soft error resilience while verifying architectural compliance

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Hobli, India

Divya Kumudprakash Joshi