International Business Machines Corporation

Qualcomm Incorporated

Divya Kumar

Edgar Rolando Cordero

Anuwat Saetow

Joab Daniel Henderson

Jeffrey A Sabrowski

Robert Brett Tremaine

Robert Walter Berry, Jr

Ryan Joseph Pennington

An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

Dual in line memory module (DIMM) connector

A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module

A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

Implementing DRAM command timing adjustments to alleviate DRAM failures

A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

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Austin, TX, United States of America

Divya Kumar