Texas Instruments Corporation

Divya Kaur

Rajat Chauhan

Santhosh Kumar Gowdhaman

Rishav Gupta

Vinod J Menezes

Muthusubramanian Venkateswaran

Vipul Kumar Singhal

Shuvam Prasad

Ashutosh Chitnis

A float detector includes a latch and a float detection circuit. The latch includes a latch output and an input/output (I/O) terminal. The I/O terminal is coupled to an input terminal. The float detection circuit includes a detection input, a drive output, and a float detection circuit. The detection input is coupled to the latch output. The drive output is coupled to the I/O terminal. The float detector is configured to provide a drive signal at the drive output, and determine that the input terminal is floating based on a latch output signal received at the detection input responsive to the drive signal.

Floating pin detection

In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.

Low noise high precision voltage reference

A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

Trim/test interface for devices with low pin count or analog or no-connect pins

In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.

Fail-safe switch for multidomain systems

A power-on-reset (POR) circuit includes an NFET branch and a PFET branch. The NFET branch includes: an n-channel field effect transistor (NFET) having a first threshold voltage; and a first quiescent bias current source coupled between a supply terminal and the NFET. The PFET branch includes: a p-channel field effect transistor (PFET) having a second threshold voltage; and a second quiescent bias current source coupled between a ground terminal and the PFET. The POR circuit is configured to provide a POR signal at an output terminal based on: the first threshold voltage or the second threshold voltage, whichever is larger; and a voltage margin. The output terminal is coupled between the PFET branch and the second quiescent bias current source.

Threshold tracking power-on-reset circuit

A device for monitoring voltage in a battery-operated system, the device including: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder includes: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder includes: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.

Voltage detector

A voltage detector circuit including a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.

A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.

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Delhi, India

Divya Kaur