Qualcomm Incorporated

Divya Gangadharan

Xiangdong Chen

Animesh Datta

Ohsang Kwon

Satyanarayana Sahu

Madan Krishnappa

Kevin Bowles

Qi Ye

Venkat Narayanan

Arvind Jain

Hong Dai

Masoud Zamani

Renukprasad Hiremath

Chih-Iung Kao

Chirag Maheshwari

Muhammad Nasir

In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

Anti-aging clock source multiplexing

An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

Integrated functional and design for testability (DFT) clock delivery architecture

A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Digital circuit design with semi-continuous diffusion standard cell

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Divya Gangadharan