Imec

Interuniversitair Microelektronica Centrum (imec)

Nxp B.v.

Stmicroelectronics Gmbh

Other

University of South Toulon Var

Imec Vzw

Stmicroelectronics N.v.

Dirk Wouters

Ludovic Goux

Gerd Norga

Gouri Sankar Kar

Mihaela Ioana Popovici

Jean-Luc Everaert

Judit Gloria Lisoni Reyes

Thomas Gille

Judit Lisoni

Pieter Blomme

Herman E Maes

Judit G Lisoni

Lucien C Van Poucke

Jan Yperman

Dirk Franco

Judit Lisoni Reyes

Ria Nouwen

Lorene Courtade

Jules Mullens

Christian Turquat

Christophe Muller

Judith Lisoni

Nicolas Menou

Jorge Kittl

The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.

Stacked RRAM array with integrated transistor selector

A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed.

Three-dimensional resistive memory array

A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85.

Method for manufacturing a resistive switching memory cell comprising a nickel oxide layer operable at low-power and memory cells obtained thereof

The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate () comprising the bottom electrode (), providing on the substrate a dielectric layer () comprising a recess () containing the metal for forming the resistive layer (), providing on the substrate a dielectric layer () comprising an opening () exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof

A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.

Method for manufacturing a resistive switching memory device and devices obtained thereof

A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized 'hot spot' is obtained.

Phase-change memory cell having two insulated regions

The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof

A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well-defined area with limited dimensions ('hot spot') than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase-change material where the resistivity is lower.

Phase-change memory cell with a patterned layer

The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug. The bottom electrode stack is prepared by depositing a ferroelectric film atop an Ir or Ru metal electrode layer, then annealing the ferroelectric layer in an oxygen ambient wherein the partial pressure of oxygen is controlled at a level sufficient to oxidize the ferroelectric layer but not at a level sufficient to oxidize the metal electrode layer.

Simplified bottom electrode-barrier structure for making a ferroelectric capacitor stacked on a contact plug

The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug. The bottom electrode stack is prepared by depositing a ferroelectric film atop an Ir or Ru metal electrode layer, then annealing the ferroelectric layer in an oxygen ambient wherein the partial pressure of oxygen is controlled at a level sufficient to oxidize the ferroelectric layer but not at a level sufficient to oxidize the metal electrode layer

A ferro-electric capacitor comprising a first electrode comprising at least a layer of a conductive oxide having at least two sub-layers of individual grains, wherein individual grains of a top sub-layer of the two sub-layers are oriented randomly. The capacitor further comprises a second electrode that is isolated from said first electrode. The capacitor further comprises a ferro-electric PZT layer that is sandwiched between said first electrode and said second electrode. A method of making the ferro-electric capacitor is also provided.

Ferro-electric capacitor and method of fabrication of the ferro-electric capacitor

The present invention is related to a method, wherein a PZT layer includes a first PZT sub-layer and a second PZT sub-layer, the Ti-concentration of the first PZT sub-layer being higher than the Ti-concentration of the second PZT sub-layer.

Method of fabrication of a ferro-electric capacitor and method of growing a PZT layer on a substrate

A method is disclosed for the formation of ferro-electric films using a multi coating process based on a sol-gel technique. In particular a method is disclosed to fabricate high-quality thickness scaled PZT films of an alkoxide-type liquid chemical PZT precursor solution, preferably a Pb(Zr,Ti,)O,precursor solution, using a sol-gel technique. At least two coated layers are deposited, but the precise number of coated layers depends on the desired thickness of the ferro-electric film. According to the method of the invention, the electrical characteristics of the film as formed are not dependent on the number of coated layers. There are a number of properties, characteristic for the method of the present invention, and resulting in said excellent electrical characteristics. In fact said method can comprise a multi coating process wherein a reduced number of coated layers is used but where intermediate crystallization steps are performed. The ferro-electric films formed using this method have excellent electrical characteristics, provided that a crystallization step is only performed if the thickness of the film formed since the last crystallization step is minimum about 40 to 50 nm. Alternatively, the method can comprise a multi coating process wherein no intermediate crystallization steps are used.

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Leuven, Belgium

Dirk Wouters