Infineon Technologies Ag

Dirk Siepe

Reinhold Bayerer

Roman Roth

Thomas Gutt

Matthias Stecher

Thomas Laska

Thomas Licht

Michael Melzl

Andreas Lenniger

Hans Hartung

A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least 10 micrometers (&#x3bc;m), the thick metal layer comprises copper or a copper alloy, and the bonding wire or ribbon comprises copper or a copper-based material.

Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate

A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 &#x3bc;m. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25&#xb0; C.

Power semiconductor module and method for operating a power semiconductor module

The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.

Method for fabricating a bond

A bonding connection between a bonding wire and a power semiconductor chip is disclosed. The power semiconductor chip has a semiconductor body arranged in which is an active cell region with a multiplicity of cells arranged one following the other in a lateral direction and connected electrically in parallel. The semiconductor body has a surface portion arranged above the active cell region in a vertical direction perpendicular to the lateral direction. Applied to the surface portion is a metallization layer onto which a bonding wire is bonded. The bonding wire comprises an alloy containing at least 99% by weight aluminum and at least one further alloying constituent. The aluminum has a grain structure with a mean grain size which is less than 2 &#x3bc;m.

Bonding connection between a bonding wire and a power semiconductor chip

A semiconductor substrate and a method for producing it is disclosed. In one embodiment, a contact region and a corresponding contact material of the semiconductor substrate are formed, in regions or completely, with a protection against oxidation.

Semiconductor module

A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (&#x3bc;m).

Semiconductor module arrangement

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Semiconductor device including a power device with first metal layer and second metal layer laterally spaced apart

The invention relates to a method and also a device and a system for bonding a semiconductor element (), in which various contact areas () of the semiconductor element () are successively connected to terminal areas () by means of bonding wire elements () and in which an electrical variable influenced by the semiconductor element () is acquired during the bonding operation.

Method, device and system for bonding a semiconductor element

One aspect relates to a bonding apparatus for producing a bonding connection between a bonding wire and a bonding partner. The bonding apparatus includes a heel shaper, which is provided for avoiding damage to the bonding wire in the heel region during the bonding operation. One aspect relates to a method for producing a bonding connection by means of a bonding apparatus having a heel shaper and a bonding stamp. The heel shaper is situated relative to the bonding stamp in a first active position or can be moved into such a first active position. In the first active position, the heel shaper ensures that the bonding wire runs in a permissible region in the heel region.

Growing community of inventors

Warstein, Germany

Dirk Siepe