Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Dirk Preikszat

Atul Ramakant Lele

Sudhanshu Khanna

John Joseph Seibold

Stefan Beierke

Norbert Asche

Imran Khan

Jozef C Mitros

Gregory Allen North

Robin Osa Hoel

Tarjei Aaberge

Oliver Nehrig

William E Nehrer

Gebhard Haug

Lou Hutter

Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

FSM based clock switching of asynchronous clocks

In an example, a system includes circuitry on a first side of an isolation barrier and circuitry on a second side of the isolation barrier, where the isolation barrier is operable to electrically isolate the first side from the second side. The system also includes a trimmed oscillator, a first transmitter, and a first receiver on the first side, the trimmed oscillator coupled to the first transmitter. The system includes a tunable oscillator, a second transmitter, and a second receiver on the second side, the tunable oscillator coupled to the second receiver and the second transmitter. In the system, the first side is configured to transmit a training sequence to the second side, and the second side is configured to tune the tunable oscillator based on the training sequence.

Clock matching tune circuit

A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

Clock oscillator control circuit

A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is formed as a loop antenna array configured to transmit and receive RFID signals. Further, the RFID tag includes a first test pad and second test pad formed on the integrated circuit die with the first test pad coupled to a first end of the antenna by a first interconnect and a second test pad coupled to the second end of the antenna by a second interconnect.

RFID tag having an integrated antenna coupled to test pads

A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is configured to transmit and receive RFID signals. Further, the antenna and the interconnects of the circuitry are formed of a same metal, and fabricated using a same semiconductor process.

RFID tag with integrated antenna

An electronic device comprising a first node to be coupled to a first antenna, a second node coupled to a second antenna, a third node to be coupled to a third antenna, a first comparator coupled with a first input to the first node and with a second input to a second node, a second comparator coupled with a first input to the first node and with a second input to the third node, a third comparator coupled with a first input to the second node and with a second input to the third node. Each of the first, the second and the third comparators are configured to compare a first current and a second current at the first input and the second input.

Electronic device and method for RFID

A semiconductor device ( ) comprising a semiconductor substrate ( ) having source and drain regions ( ) located in the semiconductor substrate ( ) and having similar doping profiles, wherein a channel region ( ) extends from the source region ( ) to the drain region ( ). The semiconductor device ( ) also comprises a dielectric layer ( ) located over the source and drain regions ( ), the dielectric layer ( ) having first and second thicknesses (T , T ) wherein the second thickness (T ) is substantially less than the first thickness (T ) and is partially located over the channel region ( ). The semiconductor device ( ) also comprises a gate ( ) located over the dielectric layer ( ) wherein the second thickness (T ) is located between an end ( ) of the gate ( ) and one of the source and drain regions ( ).

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Freising, Germany

Dirk Preikszat