Texas Instruments Corporation

Other

Dirk N Anderson

William R McKee

William F Richardson

Siang Ping Kwok

Brian Keith Kirkpatrick

Wei-Yung Hsu

Ming J Hwang

James M McDavid

Andrew McKerrow

Kenneth Joseph Newton

Michael Morrison

Mark R Visokay

Jiong-Ping Lu

Chih-Chen Cho

Clarence W Teng

Robert R Doering

Robert Kraft

Jeffrey A McKee

Wei William Lee

Ming-Jang Hwang

Jorge A Kittl

Peter S McAnally

Gishi Chung

Yin Hu

Hun-Lian Tsai

Jiong Ping Lu

Jiann Liu

Cishi Chung

A low-k dielectric layer () is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (), such as OSG, and DUV resist (). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric () before forming the pattern () or during a rework of the pattern ().

Pre-pattern surface modification of low-k dielectrics

A low-k dielectric layer ( ) is treated with a dry H plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The H plasma pre-treatment is performed to either pretreat a low-k dielectric ( ) before forming the pattern ( ) or during a rework of the pattern ( ).

Pre-pattern surface modification for low-k dielectrics using A H2 plasma

A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi N ) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The interface region is formed providing a nitrided surface layer over the exposed dielectric surfaces and the exposed substrate surface (i.e., exposed by a via in the dielectric layer) prior to the formation of tungsten/tungsten nitride layer filling the via. The structure is annealed forming a tungsten conducting plug with a tungsten-silicon-nitride interface between the conducting plug and the substrate. According to another embodiment, a tungsten nitride surface layer is formed over the nitrided surface layer prior to the formation of a tungsten layer to fill the via. According to another embodiment, a silicon surface layer is applied to the exposed surface of the dielectric layer and to the exposed surface of the substrate prior to formation of the nitrided surface layer. A layer of tungsten, tungsten/tungsten nitride, or tungsten nitride is formed to fill the via. After annealing, a tungsten conducting plug is formed with a tungsten-silicon-nitride interface region with the substrate.

Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices

The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Edge stress reduction by noncoincident layers

A method for protecting metal (,) from oxidation during various oxidation steps such as CVD SiO2 oxidation for forming an overlying oxide layer (,), smile oxidation, and sidewall (,) deposition. The gas CO2 is added to the oxidation chemistry. The CO2/H2 ratio is controlled for selective oxidation. The metal (,) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagents.

Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing

An improved method for forming a DRAM chip is disclosed. According to this method, a memory cell gate is deposited in a memory cell array area of the DRAM chip. The memory cell gate overlies a first channel area of a substrate. A peripheral gate is deposited in a peripheral area of the DRAM chip. The peripheral gate overlies a second channel area of the substrate. A first dopant is implanted with a first concentration in a first plurality of source and drain regions of the substrate lying predominantly outside the first and second channel areas of the substrate. A sidewall is then formed adjacent to the peripheral gate. Simultaneously, an insulating layer is formed over the memory cell array area of the DRAM chip. A second dopant is implanted with a second concentration in a second plurality of source and drain regions of the substrate within the peripheral area of the DRAM chip. The implant of the second dopant is blocked by the sidewall and the insulating layer. In one embodiment, the first and second dopants are the same, and the dopant concentration in the second plurality of regions is greater than the dopant concentration in the first plurality of regions. This method allows the formation of more heavily doped source and drain regions in the peripheral area of the DRAM chip while keeping the heavily doped regions separated from the channel regions. This reduces diffusion into the channel regions and allows a smaller design rule to be used.

DRAM chip fabrication method

A process for forming a W-poly gate stack (,) comprising the steps of: (1) deposition of doped polysilicon (,) on a thin dielectric layer (,) covered substrate (,), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (,) and to remove excess nitrogen and (4) deposition of W layer (,). The stack layers are then etched to form the gate electrode (,).

CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes

An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal layer and having opposing sidewalls, and a vertically oriented dielectric layer extending over and covering each of the opposing sidewalls of the barrier layer and the metal layer to encapsulate the barrier layer and metal layer on the polysilicon layer. The encapsulated gate and barrier layer are thus unaffected by oxidation and other similar detrimental effects of subsequent processing steps.

Encapsulated low resistance gate structure and method for forming same

A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).

Method for enhancing the performance of a contact

A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).

Implant screen and method

In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.

Semiconductor stack having a dielectric sidewall for prevention of

An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.

Method of manufacturing a minimum scaled transistor

A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.

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Plano, TX, United States of America

Dirk N Anderson