International Business Machines Corporation

Dirk Michel

Bret Ronald Olszewski

Mathew Accapadi

Grover Cleveland Davidson, Ii

Andrew Dunshea

Jos Manuel Accapadi

Mysore Sathyanarayana Srinivas

Vaijayanthimala K Anand

Agustin Mena, Iii

Herman Dietrich Dierks

James William Van Fleet

Bruce Gerard Mealey

Basu Vaidyanathan

Dean J Burdick

Matthew Accapadi

Diane Garza Flemming

Larry Bert Brenner

David Alan Hepkin

Matthew Ryan Ochs

Binh K Hua

Hong Lam Hua

Octavian Florin Herescu

Wen Xiong

Jean-Philippe Sugarbroad

Chad Collie

William Lee Britton

Grover C Davidson

Jean-Philipe Sugerbroad

In a computing system, an application thread is executed on a hardware thread. Based on a configuration of the computing system, a first threshold is determined comprising a threshold percentage of execution time spent servicing a set of interrupts to the application thread relative to a total execution time for the hardware thread. For the hardware thread, a length of a first time period spent servicing an interrupt in the set of interrupts and a length of a second time period spent executing the application thread are measured. A cumulative percentage of execution time spent in the first time period relative to execution time spent in the first time period and the second time period is calculated. Responsive to the cumulative percentage being above the threshold percentage, interrupt servicing on the hardware thread is disabled.

Suppressing interrupts to an application thread

Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.

Hardware thread switching for scheduling policy in a processor

According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.

Preventing software thread blocking due to interrupts

Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.

Averting lock contention associated with core-based hardware threading in a split core environment

Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking an amount of time that a lock on a first thread prevents a second thread from execution. The method also includes, if the amount of time is greater than a first threshold, storing the amount of time and an address associated with the lock. The method includes dispatching a third thread that utilizes the address associated with the lock. The method also includes increasing the hardware priority of the third thread during a lock operation.

A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.

Filtering multiple in-memory trace buffers for event ranges before dumping from memory

Mechanisms are provided for dynamically adjusting assignment of software threads to hardware threads in virtual machine (VM) environments. The mechanisms receive, by a virtual machine manager (VMM), an indication of workload priority from a plurality of VMs. The indication indicates a priority of a workload executing on each VM in the plurality of VMs. The mechanisms provide, by the VMM, an indication of physical resource usage to each VM. The indication of physical resource usage is an indication of physical resource usage across all VMs in the plurality of VMs. The mechanisms automatically adjust, by each VM, assignment of corresponding software threads to hardware threads based on the indication of physical resource usage and a priority of a workload executing on the VM to achieve a balance of usage of hardware threads across all VMs in the plurality of VMs.

Closed-loop feedback mechanism for achieving optimum performance in a consolidated workload environment

A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.

Management of file cache

Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.

Partitioned shared processor interrupt-intensive task segregator

An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.

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Austin, TX, United States of America

Dirk Michel