Infineon Technologies Ag

Qimonda Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh

Qimonda Flash Gmbh

Dirk Manger

Stefan Tegen

Till Schloesser

Michael Specht

Franz Hofmann

Rolf Weis

Till Schlösser

Matthias Goldbach

Lothar Risch

Richard Johannes Luyken

Bernd Goebel

Christoph Noelscher

Marc Probst

Frank Hoffmann

Andreas Pribil

Albert Birner

Stephan Kudelka

Wolfgang Roesner

Nicolas Nagel

Hans-Peter Moll

Christoph Ludwig

Till Schl&ouml;sser

Detlev Richter

Roman Knoefler

Martin Popp

Stephan Wege

Thomas Hecht

Klaus Muemmler

Peter Moll

Wolfgang Rösner

Stephan Riedel

Kristin Schupke

Lars Heineck

Klaus Knobloch

Stefan Slesazeck

Jörn Lützen

Dirk Caspary

Matthias Markert

Steffen Meyer

Andreas Orth

Christoph Friederich

Martin Verhoeven

Gert Koebernik

Alexander Sieck

Wolfgang Mueller

Jan Gutsche

Eike Ruttkowski

Hocine Boubekeur

Michael Sesterhenn

Srivatsa Kundalgurki

Jyoti Gupta

Hans Lindemann

Thomas Tatry

Joseph Willer

Kenny Oisin

Holger Moeller

Doris Keitel Schulz

Florian Beug

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising:

Method for manufacturing a bipolar junction transistor

A method for forming a semiconductor device includes forming a body implant region of a vertical field effect transistor arrangement in a semiconductor substrate and forming a plurality of compensation regions in the semiconductor substrate after forming the body implant region of the vertical field effect transistor arrangement. Further embodiments of methods for forming a semiconductor device are described.

Method for forming vertical field effect transistor devices having alternating drift regions and compensation regions

A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same

A semiconductor device includes a plurality of drift regions of a vertical field effect transistor arrangement arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a body region of a transistor structure of the vertical field effect transistor arrangement arranged adjacent to a drift region of the plurality of drift regions. The semiconductor device further includes a gate extending substantially vertically along the body region of the transistor structure for controlling a substantially vertical channel region between a first doping region of the transistor structure and the drift region.

Vertical field effect transistor device having alternating drift regions and compensation regions

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Integrated circuits having a contact region and methods for manufacturing the same

In a method for fabricating a capacitor that includes an electrode structure (), an auxiliary layer () is formed over a substrate (). A recess (), which determines the shape of the electrode structure (), is etched into the auxiliary layer (), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer ().

Method for fabricating a capacitor

An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Integrated circuit including a gate electrode

The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

Method of fabricating a semiconductor device

In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Method for forming a structure on a substrate and device

A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiOand SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Hard mask layer stack and a method of patterning

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Memory cell array and method of manufacturing the same

Growing community of inventors

Dresden, Germany

Dirk Manger