Texas Instruments Corporation

Other

Dirk Leipold

Robert Bogdan Staszewski

Khurram Muhammad

Chih-Ming Hung

Kenneth James Maggio

Oren E Eliezer

Sameh Sameer Rezeq

Elida Isabel De Obaldia

Renaldi Winoto

Yo-Chuol Ho

See Taur Lee

Ran Katz

John L Wallberg

Gennady Feygin

Feng Chen

Meng-Chang Lee

Wei Yu Chen

Carl Michael Panasik

James Fred Salzman

David W Evans

Alexander Mostov

Solti Peng

Robert B Staszewski

Nathen Barton

Francis P Cruise

Chandana Fernando

Nathan Barton

Elida de-Obaldia

Khurram Muhammed

A phase locked loop circuit () includes a controllable oscillator () for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit () for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator () is driven by the outputs of the first and second phase detections circuits.

Digital phase locked loop

RF circuit, DCO, frequency divider with three divided clock outputs

RF circuit with DCO, state machine, latch, modulator, timing update

First and second phase detectors and phase offset adder PLL

A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.

Digital amplitude modulation

An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (K) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (&#x394;f) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (), and the resultant dithered portion (d) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

All-digital frequency synthesis with DCO gain calculation

A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase/frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.

Simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing

Packaged integrated circuits having inductors and methods to form inductors in packaged integrated circuits are disclosed. An example method comprises forming a substrate having a first trace and a contact, attaching an integrated circuit to the substrate over the first trace, and electrically coupling the first trace to the contact via an electrical conductor that extends over the integrated circuit to form the inductor in the packaged integrated circuit.

Packaged integrated circuits having inductors and methods to form inductors in packaged integrated circuits

System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors, and) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.

Fine-grained gear-shifting of a digital phase-locked loop (PLL)

A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Radio frequency built-in self test for quality monitoring of local oscillator and transmitter

A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of 'better quality' retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

Method and apparatus for asynchronous clock retiming

The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA transceiver employing the same

Growing community of inventors

Plano, TX, United States of America

Dirk Leipold