Nxp B.v.

Dirk Kenneth De Vries

Roberto Maurizio Gonella

Albert Van De Goor

The present invention relates to a test structure that comprises at least two devices under test DUT, which respectively have a first electrical device resistance in a non-defect state and a second electrical device resistance in defect state, the first being higher than the second electrical device resistance. In the test structure the DUTs are connected in parallel to a first test contact pad via a first conducting line and connected in parallel to a second test contact pad via a second conducting line, and respectively connected to the first conducting line via respective first test resistors, which have known respective electrical test resistances, such that a total electrical resistance between the first an second test contact pads is indicative of the number of DUTs, which have the second electrical device resistance. The test structure allows testing a larger number of DUTs in parallel in a single measurement.

Test structure for detection of defect devices with lowered resistance

A method of obtaining parametric test data for use in monitoring alignment between layers of a semiconductor device. The method employs a test structure comprising a meander () of the material of a first layer of the semiconductor device, deposited relative to a conductive line (). A number of sets () of components, such as contacts or vias, are provided relative to the meander (), at successively smaller distances therefrom. A single analogue measurement can be performed between a first and (A) of the meander () and the conductive line () so as to determine the resistance therebetween, and the critical distance at (or on acceptable margin in relation thereto) between the first layer and a component of the semiconductor device can be obtained.

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St. Georges D'Orques, France

Dirk Kenneth De Vries