Advanced Micro Devices Corporation

Ati Technologies Ulc

Dirk J Robinson

Amitabh Mehra

Richard Martin Born

Anil Harwani

William R Alverson

Mikhail Rodionov

Joshua Taylor Knight

Jerry A Ahrens

Joyce Cheuk Wai Wong

Andy Huei Chu

Saket Sham Doshi

Yan Sun

The disclosed device includes a reference delay circuit for outputting a reference delay circuit output signal from a voltage regulated supply and a noisy delay circuit for outputting a noisy delay circuit output signal from a noisy or droopy supply. The device also includes a phase comparator circuit that is connected to the reference delay circuit and the noisy delay circuit. The phase comparator circuit outputs a phase difference between the reference delay circuit output signal and the noisy delay circuit output signal. Various other methods, systems, and computer-readable media are also disclosed.

Time domain-based power supply droop detector

Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

System and method for enabling clock stretching during overclocking in response to voltage droop

A clock synthesizer has integrated voltage droop detection and clock stretching. An oscillator of the clock synthesizer receives a control current from a digital to analog converter and generates an oscillator output signal. A droop detector and clock stretching circuit responds to a voltage droop of a supply voltage supplying circuits coupled to the oscillator output signal, to cause a portion of the oscillator control current to be diverted from the oscillator to thereby cause the oscillator to reduce the first frequency. The diversion can be accomplished through shunt circuits or a current mirror circuit.

Clock synthesizer with integrated voltage droop detection and clock stretching

Various semiconductor chip clock signal pathways are disclosed. In one aspect, a semiconductor chip with a receiver includes a clock signals pathway for conveying plural clock phases in the receiver. The clock signals pathway includes plural wires in an arrangement that has a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge. Each of the wires conveys a clock phase. The wires of the arrangement are routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline.

Low-power multi-phase clock distribution on silicon

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Ft. Collins, CO, United States of America

Dirk J Robinson