Infineon Technologies Ag

Dirk Fuhrmann

Reidar Lindstedt

Norbert Rehm

Jan Zieleman

Rath Ung

Rob Perry

Robert C Perry

Martin Perner

Matthias Skalitz

A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

Random access memory including circuit to compress comparison results

An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock generator circuit. The supply voltage is provided by a controllable voltage generator that includes a controllable resistor. During the production process, the supply voltage generated can be picked up at a contact pad. The value of the controllable resistor is changed in each memory chip by an automatic production machine until the supply voltage generated matches a target value. The controllable voltage generator can be adjusted individually for each memory chip via fuse elements so that the target value of the supply voltage is achieved with high accuracy for each memory chip.

Integrated semiconductor memory with adjustable internal voltage

Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.

Test parallelism increase by tester controllable switching of chip select groups

An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to the first bit line. When writing/reading the first memory state, the sense amplifier produces a negative voltage at the first output connection and a positive voltage at the second output connection, and when writing/reading the second memory state, it produces the positive voltage at the first output connection and the negative voltage at the second output connection. The production of a negative voltage results in one of the two bit lines being charged approximately to a ground potential during a read or write access.

Integrated semiconductor memory device

An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

Integrated semiconductor memory with temperature-dependent voltage generation

A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.

Random access memory including first and second voltage sources

A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer

An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

Method for testing an integrated semiconductor memory with a shortened reading time

A semiconductor arrangement on a semiconductor chip includes a number of lines of a first type that extend outwardly from an inner region toward an outer region of the semiconductor chip. A number of lines of a second type are arranged around the inner region of the semiconductor chip. The lines of the second type are bit lines when the lines of the first type are word lines and the lines of the second type are word lines when the lines of the first type are bit lines. A number of individual element arrays are arranged along the lines of the first type and lines of the second type. The individual element arrays include memory cells.

Semiconductor arrangement

An integrated memory contains an addressing unit for addressing memory cells for a memory access on the basis of received addressing signals. An addressing calculation logic unit is connected to the addressing unit. The latter can be activated by a test mode signal for a test operation of the memory. The addressing calculation logic unit receives command signals and address signals for the test operation, calculates therefrom the addressing signals for the memory access and feeds the latter into the addressing unit. After an initialization with the loading of initial parameters, the command signals and address signals for the test operation are applied to the addressing calculation logic unit and read/write operations are carried out by an access controller. An integrated memory with implemented BIST hardware, in the case of which a comparatively high functionality and flexibility during the memory test, are nevertheless made possible.

Integrated memory and method for checking the functioning of an integrated memory

A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which the memory cells are connected that are curved. Combining the geometry of the memory cell array with storage capacitors laterally offset allows signal delays along word lines and bit lines to be aligned regardless of the position of a memory cell in the memory cell array. The geometry of the memory cell array allows short signal propagation times to be attained particularly along the first lines, which are divergent with respect to one another, this simplifying error-free operation of a semiconductor memory particularly at high clock frequencies.

Semiconductor memory having an arrangement of memory cells

An integrated semiconductor memory that can be tested includes a control circuit and a memory cell having a selection transistor. In a normal operating mode, the integrated semiconductor memory can be controlled by applying control signals and can be switched from a normal operating mode to a test operating mode by the applying a signal combination of the control signals. In the test operating mode, the control circuit interprets a first of the control signals as a signal for turning off the selection transistor and a second of the control signals or a signal combination of the control signals as a signal for switching the selection transistor into the on state. The method enables the testing of different times between reading a data set into the memory cell and turning off the selection transistor.

Method for testing an integrated semiconductor memory, and integrated semiconductor memory

A semiconductor memory has a novel geometry of a memory cell array. Without reducing the distance between storage capacitors that are the most closely adjacent to one another it is possible to structure additional lines between adjacent lines in particular word lines. In a preferred embodiment, the number of word lines required for the number of memory cells remaining the same is reduced, as a result of which word line drivers are saved and substrate area is gained.

Growing community of inventors

Essex Junction, VT, United States of America

Dirk Fuhrmann