Infineon Technologies Ag

Qimonda Ag

Dirk Caspary

Stefano Parascandola

Nicolas Nagel

Dirk Manger

Roman Knoefler

Christoph Nölscher

Stephan Riedel

Dominik Olligs

Arnd Scholz

Matthias Markert

Martin Verhoeven

Torsten Mueller

Hocine Boubekeur

Thomas Tatry

Dorit Kaulfuss

A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

Methods of manufacturing semiconductor structures

A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiOand SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Hard mask layer stack and a method of patterning

The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

Semiconductor memory device and method of production

Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.

Method of production pitch fractionizations in semiconductor technology

Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.

A method and a device for sorting wafers from an initial state into an end state. The wafers are at least partly identifiable as elements of a finite sequence based on an information carrier. In the initial state, the wafers are arranged in any desired sequence in compartments of a holding device and in the end state each wafer is arranged in accordance with its position in the sequence in the compartments of the holding device. The first wafer is removed from a first compartment of the holding device. The information carrier of the first wafer is read by a reading device to determine the position of the first wafer in the sequence. Subsequently, a second wafer is removed from a second compartment corresponding to the position of the first wafer in the sequence. The first wafer is moved into the compartment corresponding to its position in the sequence.

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Dresden, Germany

Dirk Caspary