Freescale Semiconductor,inc.

Plantronics, Inc.

Freescale

Dipesh Koirala

Dana John Taipale

Christopher P Thron

Joseph Samuel

Krishna Balusu

Chris P Thron

Subrahmanya Srinivasulu Hari

Peter Tao

A system which automatically provisions teleconferencing equipment with virtually all necessary settings is provided. The need for end users to spend time manually configuring such equipment to use the services of a teleconferencing service provider is, in most cases, eliminated.

Streamlined provisioning for teleconferencing endpoints

A method for efficiently calculating signal thresholds for use in signal processing is described. The method computes and stores a cumulative histogram and a weighted cumulative histogram. The method then provides a first estimate for a threshold based on a single ratio. The method next performs an iterative computation to get to the ultimate threshold result. Method iterations only require multiplication and addition operations on the stored values making the method well suited for implementation in fixed-point digital signal processors.

Efficient fixed-point real-time thresholding for signal processing

An integrated circuit arranged and constructed to determine an upper data rate for a variable data rate signal and method thereof includes a buffer, comparator, and combiner that are operable to compare a characteristic, such as an energy statistic of a number of partial symbols constructed from the variable data rate signal to a first threshold that corresponds to the number to provide a first comparison; process the variable data rate signal at a first data rate when the first comparison is favorable; compare the characteristic to a second threshold that corresponds to the number to provide a second comparison; and combine the partial symbols to provide other partial symbols at a second data rate that is less than the first data rate when the second comparison is favorable.

Method and apparatus for determining an upper data rate for a variable data rate signal

A Code Division Multiple Access (CDMA) post-correlation processing system () for delay locked loop processing reduces the control data rate into a delay locked loop (DLL) processor and the number of required interpolation operations by executing a portion of the interpolation operations at a symbol data rate rather than at a chiprate. Specifically, an interpolator () generates time shifted chip samples based on input CDMA chip samples. First and second correlators () extract ontime control and data symbol samples, respectively, from ontime input CDMA chip samples. A third correlator () extracts first non-ontime control symbol samples from non-ontime CDMA chip samples. The first non-ontime control symbol samples are then input with the ontime control symbol samples to a post-correlation interpolator () operating at a symbol rate to generate second non-ontime symbol samples necessary for Delay Locked Loop (DLL) processing.

Growing community of inventors

Austin, TX, United States of America

Dipesh Koirala