Synaptics Corporation

Nvidia Corporation

Gainspan Corporation

Dipankar Talukdar

Atul Garg

Ignatius B Tjandrasuwita

Jonathan Losh

Iole Moccagatta

Shankar Moni

Sandeep Shyamsukha

Takashi Nose

Hirobumi Furihata

Guozhong Shen

Masao Orio

Akio Sugiyama

Chirinjeev Singh

Kota Kitamura

Alan J Herring

A processing system configured to receive a first display control signal corresponding to a non-display update period of a display frame and a second display control signal corresponding to a display update period of the display frame. The processing system is further configured to acquire, based on receipt of the first display control signal, first resulting signals from sensor electrodes electrically connected to the sensor driver by operating the sensor electrodes for a first type of input sensing during a first period overlapping with at least a portion of the non-display update period. Further, the processing system is configured to acquire, based on receipt of the second display control signal, second resulting signals with the sensor electrodes by operating the sensor electrodes for a second type of input sensing during a second period overlapping with at least a portion of the display update period.

Synchronizing input sensing with display updating

A display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and generate second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period.

Built-in test of a display driver

A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.

External memory tagging and stack ordering of memory tags

The present invention includes a method and system for encoding video data by accessing a picture to be encoded, wherein the picture comprises a plurality of macro-blocks. A plurality of programmable counters are associated with each macro-block to be encoded. A counter associated with a macro-block of the plurality of macro-blocks is accessed and a value of the counter is determined. The method further includes determining whether to encode the macro-block as an Intra or non-Intra based on the value of the counter. If the macro-block is encoded as Intra, its counter is reset. If the macro-block is encoded as non-Intra, its counter value is updated. The counter value may be reset with a random number. Counters can be programmed such that a region of interest is defined for updating associated macro-blocks with greater frequency.

System and method for intra refresh implementation

System and method for intra refresh implementation with pseudo random number generation

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San Jose, CA, United States of America

Dipankar Talukdar