Intermolecular, Inc.

Synopsys, Inc.

Kabushiki Kaisha Toshiba

Vlsi Technology, Inc.

Sandisk 3d LLC

Northrop Grumman Systems Corporation

Cadence Design Systems, Inc.

Other

Koninklijke Philips Corporation N.v.

Globalfoundries Inc.

Philips Electronics North America Corporation

First Solar, Inc.

Numerical Technologies, Inc.

Vlsi Technologies, Inc.

Intermoecular, Inc.

Dipankar Pramanik

Victor Moroz

Tony P Chiang

Xi-Wei Lin

Sergey V Barabash

Yun Yu Wang

Imran Hashim

Takeshi Yamaguchi

Tim Minvielle

Vivek Jain

Vidyut Gopal

Subhash R Nariani

Mankoo Lee

Milind Ganesh Weling

Calvin T Gabriel

David E Lazovsky

Kuang-Yeh Chang

Hieu T Pham

Hong Sheng Yang

Xuena Zhang

Charlene Chen

Andrew Steinbach

Subhas Bothra

Jyh-Chwen Frank Lee

Abdurrahman Sezginer

Prashant B Phatak

Mark Harold Clark

Ashish Bodke

Kevin Kashefi

Satyendra S Sethi

Daniel C Baker

Kouros Ghandehari

Roy Varada Prasad

Kishore Singhal

Michael Sanie

Michiel Victor Paul Kruger

Chris Kirby

Tony Chiag

Xi Wei Lin

Bin Yang

Philip Allan Kraus

Minh Le

Zhi-Wen Sun

Olov B Karlsson

John S Foster

Frank Greer

Amol Ramesh Joshi

Mark V Raymond

Harlan Lee Sur, Jr

Samit S Sengupta

Amir Bayati

Minh Anh Nguyen

Zhendong Hong

Sandip Niyogi

Usha Raghuram

David Chi

Xiaopeng Xu

Bei Li

Olivier F Laparra

Jingang Su

Boris Borisov

Ed Korczynski

Susan Jennifer Lippincott

Milind G Weiling

Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Hydrogenated amorphous silicon dielectric for superconducting devices

A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

Method for suppressing lattice defects in a semiconductor substrate

Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Analysis of stress impact on transistor performance

Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

Superconducting circuits with reduced microwave absorption

Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blend crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Zinc blende cadmium&#x2014;manganese&#x2014;telluride with reduced hole compensation effects and methods for forming the same

Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300&#xb0; C. to about 600&#xb0; C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600&#xb0; C. to about 850&#xb0; C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Method for forming metal oxides and silicides in a memory device

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Photo-induced MSM stack

An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Creating an embedded ReRAM memory from a high-k metal gate transistor structure

A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (&#x394;fG&#xb0;) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiOinterfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Nonvolatile resistive memory element with an oxygen-gettering layer

An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (&#x3c;350 C, e.g. &#x2dc;200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., &#x3c;350 C) or impact to passivate defects such as dangling bonds.

Fluorine passivation of dielectric for superconducting electronics

The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

System and method for modifying a data set of a photomask

A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

Multi-level memory array having resistive elements for multi-bit data storage

A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Electrode for low-leakage devices

Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can include insulator layers between the semiconductor layer and the metal layers to lower the leakage current of the device. The metal layers of the selector element can include conductive materials such as tungsten, titanium nitride, or combinations thereof.

Tunneling barrier creation in MSM stack as a selector device for non-volatile memory application

Provided are method for determining switching conditions for production memory cells based on dopant flux during set and reset operations. One group of test memory cells, which are representative of the production memory cells, is subjected to a prolonged application of a set voltage, while another group is subjected to a prolonged application of a reset voltage. Different durations may be used for different cells in each group. A dopant concentration profile of a test component in each cell is determined for both groups. One cell from each group may be identified such that the changes in the dopant concentration profiles in these two identified cells are complementary. The profile complementarity indicates that these two identified cells had a similar dopant flux during voltage applications. Durations of set and reset voltage applications for these two cells may be used to determine switching conditions for production memory cells.

Switching conditions for resistive random access memory cells

Growing community of inventors

Saratoga, CA, United States of America

Dipankar Pramanik