Texas Instruments Corporation

Pulsecore Semiconductor, Inc.

Dipankar Mandal

Kiran Godbole

Nagesh Surendranath

Subramanian Jagdish Narayan

Dan I Hariton

Narendar Venugopal

Janakiraman Seetharaman

Akhila Gundavarapu

Dileep Kumar R

Sushil Kumar

Srihari Varma Datla

Werner Hoeft

Prathamesh Pilankar

In an example, a system includes a first transistor having a first terminal coupled to a current mirror and a control terminal coupled to a first current source and a resistor. The system includes a second transistor having a first terminal coupled to the current mirror, a second terminal coupled to a second terminal of the first transistor, and a control terminal coupled to the resistor and a second current source. The system includes a third transistor having a first terminal coupled to a voltage terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the first terminal of the second transistor. The system includes a fourth transistor having a control terminal coupled to the current mirror, first and second terminals coupled to one another and to the second terminal of the first transistor.

Oscillator frequency based on mobility and PTAT temperature compensation

A floating input detection method and circuits. A method for detecting a floating signal input terminal includes providing a common-mode input voltage to a first amplifier coupled to the signal input terminal, and providing an output signal generated by the first amplifier to: a non-inverting input of a second amplifier coupled to the signal input terminal, an inverting input of the second amplifier, coarse detection circuitry, and fine float detection circuitry. The method also includes comparing, by the coarse detection circuitry, the output signal to a first threshold voltage, and determining the signal input terminal to be not floating responsive to the comparing indicating that the output signal is greater than the first threshold voltage.

Floating input detection

Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Frequency detector and oscillator circuit

The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is coupled to the comparator, and receives one of an input voltage and a set of reference voltages. A set of M offset capacitors is coupled to the comparator, and receives one of a primary voltage and a secondary voltage, M is an integer. A difference in the primary voltage and the secondary voltage varies linearly with temperature.

Method and apparatus for compensating offset drift with temperature

A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation.

System and method for multi channel sampling SAR ADC

For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors.

Multi-channel SAR ADC

Because of variations in open loop gain and bandwidth in successive approximate register (SAR) analog-to-digital converters (ADCs), designing amplifiers with the desired characteristics is difficult. Here, a multipath amplifier is provided that accounts for the variations in open loop gain and bandwidth. Preferably, a number of cascaded amplifiers are provided that can auto-zero to account for offset voltages so as to allow the multipath amplifier to be stable over the desired open loop gains and bandwidths.

Multipath amplifier

A controllable delay clock buffer that provides spread spectrum modulation of the output signals with zero cycle slip includes a PLL having a PLL loop filter that comprises an RC network. A clock signal is input to the PLL, and a SS modulation frequency is injected into the capacitor of the PLL loop filter. The SS signal is provided by a secondary charge pump that produces a programmable waveform such as a square wave or a stair case square wave current signal. The programmable waveform is integrated by the loop filter capacitor to form a corresponding triangular or trigonal waveform which varies the input to the VCO of the PLL to define a frequency modulation profile that has a corresponding triangular or trigonal envelope. The bandpass profile of the SS modulation signal is at a higher frequency range than the lowpass profile of the PLL, so that the SS waveform profile is not distorted or cancelled by the PLL.

Spread spectrum controllable delay clock buffer with zero cycle slip

A sampling circuit according to correlated double sampling to generate a difference of two voltages at a sampling node, with the second voltage representing the sum of an input signal and an offset, and the first voltage representing the offset alone. In an embodiment, a first capacitor is charged to the first voltage in a first phase. A second capacitor is then charged to the second voltage in a second phase. In a third phase, the first capacitor is coupled to the input terminal of the amplifier and the second capacitor is coupled between the input and output terminals of the amplifier to cause the amplifier to generate the difference of the first and second voltages. The first capacitor has a capacitance much less than the second capacitor, thereby minimizing the noise power at the output of the amplifier.

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Dipankar Mandal