Opti, Inc.

Dipankar Bhattacharya

Subir K Ghosh

Mark R Williams

Sukalpa Biswas

A host-bus-to-PCI-bus bridge circuit waits until the PCI-bus clock cycle in which the PCI-bus data transfer corresponding to a current data write access on the originating bus actually takes place, before deciding whether a next data write access is pending on the originating bus and is burstable on the PCI-bus with the current data write access. If so, then the bridge continues the burst with the data of the new data write access. If not, the bridge terminates the PCI-bus burst write transaction by asserting IRDY# and negating FRAME# for the immediately subsequent PCI-bus clock cycle. A final data phase takes place on the PCI-bus in response to these actions, but all data transfer is inhibited because the bridge negates all of the byte-enable signals (BE#(3:0)). An increased likelihood results that successive data write accesses on the originating bus can be collected into a single burst transaction on the PCI-bus.

System for controlling variable length PCI burst data using a dummy

Method and apparatus for arbitrating for a shared resource among two or more devices, wherein one device can arbitrate at two or more different levels of priority at different times. Only two conductors are used to communicate between the device and the arbiter: one request signal line and one grant signal line. In order to assert a request for control of memory, the device brings the request signal line to a predefined logic level. The arbiter considers this a low priority request for control of the shared resource, and the arbitration proceeds accordingly. Then, if the device's request is a high priority request, or if it was originally a low priority request and has now become a high priority request, the device brings the request signal to the opposite logic level to thereby increase the priority level of its request. In either case, the arbiter grants control of the shared resource by asserting the device grant signal to the device. Only two wires are required for the dual priority device to participate in the arbitration.

Method and apparatus for arbitrating requests at two or more levels of

An EISA-compatible computer system having an arbitration mechanism which incorporates a programmable hold delay register and counter for delaying a CPU hold request (DHOLD) by a programmable number of BCLK cycles after an EISA device wins the top level and CPU/EISA level arbitration. The CPU hold request is not delayed if a DMA/ISA device wins the arbitration.

Programmable hold delay

Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Adaptive write-back method and apparatus wherein the cache system

According to the invention, roughly described, the EISA arbitration scheme is used for arbitrating among a plurality of requestors for a system bus, the requestors including the CPU, a refresh controller, EISA devices and ISA/DMA devices. A refresh control signal is asserted if the refresh controller wins the arbitration, and a CAS# before RAS# refresh is performed on local memory in response to the refresh control signal after completion of any CPU access to local memory then taking place. The CPU can continue to access external cache during system bus refresh, and a CPU access to local DRAM is delayed only by the amount of time required for the shorter local DRAM refresh to complete.

Method and apparatus for local memory and system bus refreshing with

Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies. In another aspect, for events to be generated on a destination bus synchronously with a clock signal which is by specification stretchable, the destination bus event is generated promptly in response to the originating event and then the destination bus clock signal is stretched to make the destination bus event synchronous with the destination bus clock signal. The length of the stretch is responsive to the relative frequencies of the originating bus and destination bus clock frequencies. A synchronizer is used to generate the destination bus event synchronously with the destination bus clock signal. The user of the chipset can select which formula is to be applied.

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Santa Clara, CA, United States of America

Dipankar Bhattacharya