Intel Ndtm US LLC

Dipanjan Basu

Ali Khakifirooz

Fei Wang

Jie Li

Rohit Sudhir Shenoy

Meng-Wei Kuo

Sung-Taeg Kang

Randy Koval

Henok Mebrahtu

Minsheng Wang

Xingui Zhang

Guanjie Li

Qun Gao

Rifat Ferdous

Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

Metal hybrid charge storage structure for memory

At the end of or after a reading operation in a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a high voltage at the end or after the reading operation and then transition a selected wordline of the multiple wordlines from the high voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the high voltage to ground after a delay.

Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array

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Portland, OR, United States of America

Dipanjan Basu