Agilent Technologies, Inc.

Ramtron International Corporation

Enhanced Memory Systems, Inc.

Dion Nickolas Heisler

James Dean Joseph

Doyle James Heisler

Nimal K K Gamage

A test probe. The test probe includes an interconnect module configured to connect to a modular, replaceable wireless module, a connect module configured to communicate with a communication network and the wireless module, an identification module configured to receive and transmit an identification of the test probe, an audio module configured to enable transfer of audio data from/for communication with the communication network from/to the wireless module and to translate audio data to/from audio signals, and a computer configured to enable transfer of audio signals from/to the audio module, transfer of digital data from/to the wireless module, and transfer of test data to/from a remote controller. Test data from the remote controller comprises instructions to control the wireless module and data for the wireless module to transfer to the connect module, and test data transmitted to the remote controller comprises digital data and audio data received from the wireless module.

Test probe having modular components

An interface module. The interface module includes a probe identification module configured for connection to an identification bus, a probe detect module configured for connection to a detect-control bus, a power control module configured for connection to the detect-control bus, a control and data module configured for connection to a control-data bus, and multiple connectors. Each connector has an associated hot swap circuit. For each connector, if the probe detect module detects connection of that connector to a test probe via connection of that connector to the probe detect module, the probe identification module is configured to enable transfer of an identification label identifying that test probe to that test probe via that connector and the control and data module is configured to enable transfer of control instructions and data between the control-data bus and the test probe via connection of the control and data module to that connector.

Interface for detection and control of multiple test probes

The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.

EDRAM having a dynamically-sized cache memory and associated method

An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.

EDRAM with integrated generation and control of write enable and column

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

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Colorado Springs, CO, United States of America

Dion Nickolas Heisler