Motorola Corporation

Audio Digital Imaging Inc.

Dion D Messer

Sangil Park

Charles D Thompson

Midori J Monroe

A parallel processing building block (PPBB) chip comprises a low performance programmable digital signal processor (DSP) to implement relatively low intensity processing functions and includes a bus control for address and data communication. A medium performance programmable DSP to implement relatively medium intensity processing functions and includes a bus control for address and data communication. A high performance programmable DSP to implement relatively high intensity processing functions and includes a bus control for address and data communication. A serial and parallel bus controller provides external connectivity to a host system bus. A data router controller is connected to the bus control of each of the high, medium and low DSP's, and to the bus controller, and includes a memory interface controller for connection to an external RAM system, and a data router for controlling data movement between any of the high, medium and low DSP's, the memory interface controller, the bus controller as well as to other PPBB chips.

Parallel processing building block chip

A receiver (20) digitally tunes a radio frequency (RF) signal at the same time that it mixes the RF signal to a frequency suitable for demodulation and channel separation. A clock frequency divider (35) receives a reference clock signal, and divides the reference clock signal to provide a divided signal at a predetermined frequency, such as 20 kHz for AM stereo. A clock frequency multiplier (36) receives the divided signal and a digital tuning input signal, and provides an analog tuning signal at a multiple of the divided signal as determined by the digital tuning input signal. An analog multiplier (31) then mixes the RF signal with the analog tuning signal. An analog-to-digital converter (ADC) (32) receives an output of the analog multiplier (31), and is clocked by the reference clock signal to eliminate any clock phase error. A digital demodulator (38) then demodulates and further processes an output of the ADC (32).

Receiver with digital tuning and method therefor

A analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), and A/D converter (18), an oscillator (12) and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.

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Austin, TX, United States of America

Dion D Messer