Synopsys, Inc.

Dino Anthony Toffolon

Scott Lawrence Howe

Adam Burns

Cameron Lacy

Euhan Chong

John Theodore Stonick

Michael W Lynch

Ayal S Shoval

Edvard Mkrtchyan

Jasjeet Singh

Jianping Wen

Daniel Keith Weinlader

David Andrew Yokoyama-Martin

Skye Wolfer

James P Flynn

Carlos Azeredo Leme

Davit Petrosyan

Richard H Steeves

Nelson S H Lam

Chris Dietrich

Nacer Eddine Belabbes

Morten Christiansen

Tom Thomas

Jin Chen

Andrew Chung Chun Lam

Nelson Lam

A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Phase mixer non-linearity measurement within clock and data recovery circuitry

A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Phase mixer non-linearity compensation within clock and data recovery circuitry

Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known relationship with a second voltage value that is used as a reference voltage in the second device. The offset circuitry can then determine the second voltage value from the second voltage signal, and output an offset value based on a difference between the first voltage value and the second voltage value.

Ground offset monitor and compensator

A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.

Two-part interface PHY for system-on-chip devices

Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation.

Calibration unit for calibrating an oscillator, oscillator arrangement and method for calibrating an oscillator

Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f, and the second node can output a second signal having frequency fthat is different from f. In some embodiments, a frequency divider can generate a third signal having frequency fbased on the second signal. In some embodiments, a frequency divider can generate the first signal based on a reference signal having frequency f. The programmable phase rotator can be capable of updating, at an update frequency that is substantially equal to fand/or f, a phase difference between the first signal and the second signal. In some embodiments, the circuit can be part of a USB (Universal Serial Bus) 3.0 physical layer (PHY) circuit.

Fractional frequency division or multiplication by using an oversampled phase rotator for reducing jitter

One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency fby varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f=f/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

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A 'supply-less' transmitter output stage is provided for a transmitter. This transmitter output stage can include a tunable source termination and a reference voltage generator. The tunable source termination can be coupled between a differential pair of the transmitter. The reference voltage generator can advantageously generate reference voltages from a far-end termination. These reference voltages provide a way of translating the internal supply voltage level to the pad voltage level to enable/disable the tunable source termination. Also, it provides a way to minimize leakage and minimize the junction stress of switching transistors in the tunable source termination as well as the transmitter. The dependency between the reference voltages and the far-end termination voltage makes this design more portable to other supply voltages and other technologies specifications other than HDMI.

'Supply-less' HDMI source terminated output stage with tuned wide-range programmable termination

Embodiments of the present invention provide a voltage regulator. The voltage regulator includes a driving mechanism coupled to an output node (VREG), wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node. In addition, the voltage regulator includes a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in the output node voltage when a load coupled to the output node requires a transient switching current that is faster than the loop response time of the driving mechanism. Furthermore, the boost circuit is biased using a self-tracking mechanism to provide accurate duration and level of the current to the output node in a transient switching event.

Voltage regulator with ripple compensation

A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D&#x2212; signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45&#x3a9;&#xb1;10%) in the USB transceiver.

USB 2.0 HS voltage-mode transmitter with tuned termination resistance

Embodiments of the present invention provide a system that controls noise in a power system that includes a power rail and a ground rail. The system includes a MOS transistor coupled in series with a decoupling capacitor between the power rail and the ground rail and an inductive packaging connection coupled to the power rail in parallel with the MOS transistor and the decoupling capacitor. The combination of MOS transistor, decoupling capacitor, and inductive packaging connection form a resonant circuit. During operation, the system determines if there is noise in a Vsignal on the power rail. Based on the noise present in the Vsignal, the system adjusts the impedance of the MOS transistor to reduce the noise in a frequency range near a frequency of interest (&#x3c9;) of the resonant circuit without causing an unnecessary increase in switching noise at other frequencies.

Variable-impedance gated decoupling cell

A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D&#x2212; signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 &#x3a9;&#xb1;10%) in the USB transceiver.

Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit.

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Stoney Creek, Canada

Dino Anthony Toffolon