International Business Machines Corporation

Advanced Micro Devices Corporation

Dinkar Virendra Singh

Zhibin Ren

Jeffrey W Sleight

Toshiharu Furukawa

Alfred Grill

Wilfried Haensch

Anthony I Chou

Leathen Shi

Kathryn Wilder Guarini

Ghavam G Shahidi

Kevin K Chan

Katherine Lynn Saenger

Amlan Majumdar

Deborah A Neumayer

Steven John Koester

Vishnubhai Vitthalbhai Patel

Xinhui Wang

Erin C Jones

John Michael Hergenrother

Antonio F Saavedra, Jr

Louis L Hsu

Judson Robert Holt

Renee Tong Mo

Li-Kong Wang

Ashima B Chakravarti

Woo-Hyeong Lee

Gen Pei

Suk Hoon Ku

Ryan Matthew Mitchell

Jeremy John Kempisty

A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.

Control of carbon nanotube diameter using CVD or PECVD growth

Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX)

An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.

Ultrathin SOI CMOS devices employing differential STI liners

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension

A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.

Method for improving semiconductor surfaces

Described is a wet chemical surface treatment involving NHOH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO) at low temperatures (less than or equal to 400&#xb0; C.). Surface energies as high as &#x2dc;4835&#xb1;675 mJ/mof the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000&#xb0; C.). Void free bonding interfaces with excellent yield and surface energies of &#x2dc;2500 mJ/mhave also be achieved herein.

Low temperature fusion bonding with high surface energy using a wet chemical treatment

A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.

Selective incorporation of charge for transistor channels

A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Enhanced T-gate structure for modulation doped field effect transistors

Growing community of inventors

White Plains, NY, United States of America

Dinkar Virendra Singh