International Business Machines Corporation

Globalfoundries Inc.

Dinh Dang

Jeffrey C Maling

Thai Doan

Steven M Shank

Bruce Walter Porth

June Cline

Jessica A Trapasso

Mark Lagerquist

Lisa Y Ninomiya

Anthony K Stamper

Qizhi Liu

Alvin Jose Joseph

James Albert Slinkman

James Stuart Dunn

Alan Bernard Botula

Max Gerald Levy

Peter James Lindgren

Ramana Murty Malladi

Mattias E Dahlstrom

Jessica Anne Levy

Alan Frederick Norris

Zhong-Xiang He

Christopher Vincent Jahnes

Edward Crandal Cooney, Iii

Eric Jeffrey White

William Joseph Murphy

Russell T Herrin

Timothy E Neary

Gary L Milo

Paul William Pastel

Arthur C Winslow

John G Twombly

David A DeMuynck

George A Dunbar, Iii

Sarah A McTaggart

Michael E Bailey

James George Michael

Melissa J Roma

Sylvia R Tousley

Thomas W Weeks

Jeffrey L Thompson

A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Metal wires of a stacked inductor

A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Device isolation with improved thermal conductivity

Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Planar cavity MEMS and related structures, methods of manufacture and design structures

A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Low harmonic RF switch in SOI

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

SOI substrate contact with extended silicide area

A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

Deep trench in a semiconductor structure

A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

Deep trench formation in semiconductor device fabrication

A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.

In a plasma or RIE etching tool using a uniquely designed annulus around a wafer supporting pedestal, it has been found that the introduction of one or more gases in the region immediately adjacent the annulus controls the amount of etching of features in that region in the surface of the wafer mounted on the pedestal. By so controlling the amount of gas in this region, the slope of the walls of the etched features can be also controlled.

Symmetrical etching ring with gas control

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Essex Junction, VT, United States of America

Dinh Dang