Hewlett-packard Development Company, L.P.

Tensilica, Inc.

Hewlett-packard Company

Ding-Kai Chen

Christopher Rowen

Dror E Maydan

David W Goodwin

Darin Stamenov Petkov

Peng Tu

Steven Weng-Kiang Tjiang

Dz-Ching Ju

A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Automatic instruction set architecture generation

System and method are described for register optimization during code translation utilizes a technique that removes the time overhead for analyzing register usage and eliminates fixed restraints on the compiler register usage. The present invention for register optimization utilizes a compiler to produce a register usage bit vector in a NOP instruction within each basic block (i.e., subroutine, function, and/or procedure). Each bit in the bit vector represents a particular caller-saved register. A bit is set if, at the location of NOP instruction, the compiler uses the corresponding register within that basic block containing the NOP instruction to hold information to be used at a later time. During the translation, the translator examines the register usage bit vector to very quickly determine which registers are free and therefore can be used during the register optimization without the need to save and restore the register values.

System and method for efficiently passing information between compiler and post-compile-time software

Apparatus and method are described for register optimization during code translation and utilizes a technique that removes the time overhead for analyzing register usage, and eliminates fixed restraints on the compiler register usage. The present invention for register optimization utilizes a compiler to produce a bit vector for each program unit (i.e., subroutine, function, and/or procedure). Each bit in the bit vector represents a particular caller-saved register. A bit is set if the compiler uses the corresponding register within that program unit. During the translation, the translator examines the bit vector to very quickly determine which registers are free, and therefore can be used during register optimization without having to save and restore the register values.

Apparatus and method for efficiently obtaining and utilizing register usage information during software binary translation

Apparatus and method are described for fast code coverage analysis. The present invention for fast code coverage analysis utilizes a technique that provides for capturing an event every first time that a block of code is visited. This allows for generating an event only once during numerous executions of a code block. The generation of only one event provides for an execution time close to the speed of the original source code.

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San Jose, CA, United States of America

Ding-Kai Chen