Taiwan Semiconductor Manufacturing Comp. Ltd.

Ding-Dar Hu

Lee-Chung Lu

Yuan-Chang Huang

Chwen-Ming Liu

Mei-Yen Li

Chia-Lin Cheng

Jiann-Jong Wang

Li-Chun Chen

Chih-Ming Huang

Chao-Ray Wang

Li-chun Chen

Hong-Che Hsiue

Horng-Jer Hsiue

Ching-Kunn Huang

An integrated circuit for routing of an electrical connection include a first metal layer having a first set of dummy conductive segments discretely arranged, and a second metal layer having a second set of dummy conductive segments discretely arranged. The segments of the first and second sets are interleaved with vertically overlapped areas for providing a predetermined link path between a selected first and a selected second nodes on two dummy conductive segments by selectively connecting a predetermined subset of the first and second dummy conductive segments through their vertically overlapped areas.

Integrated circuit design for routing an electrical connection

An integrated defect yield management and query system for a semiconductor wafer fabrication process is disclosed. A local area network connects various testing devices for testing defect conditions of wafers, a defect yield management server and a client device. After inspection, these devices generate a plurality of process records corresponding to each of the semiconductor wafers. The defect yield management server retrieves the process records through the local area network. These process records are stored in a database divided into a plurality of fields, wherein each field corresponds to a specific defect property of the semiconductor wafers. Therefore, these acquired on-line data and their related history records can be accessed by using an inquiring interface, and the client device can effectively poll the process records stored in the database of the defect yield management server.

Integrated defect yield management and query system

A process for forming a low resistance, titanium silicide layer, for use as a component of a narrow width, polycide gate structure, has been developed. The process features a combination of ion implantation procedures, performed prior to, and after, titanium deposition. The combination of ion implantation procedures restricts excessive movement of silicon, from a polysilicon gate structure, as well as from a source/drain region, into the forming titanium silicide layer, during subsequent anneal cycles used to form the titanium silicide layer. The ability to limit the amount of silicon, in the titanium silicide layer, allows a low resistance, titanium silicide layer to be used for polycide gate structures, with a width narrower than 0.20 micrometers.

Advanced titanium silicide process for very narrow polysilicon lines

The present invention provides a method for performing a pre-amorphization implant which reduces damage to the resist protect oxide layer and reduces leakage current between the gate and substrate. Two novel approaches are provided, both of which use a photoresist mask to protect the RPO from implant damage during PAI. In the first approach, the PAI is performed immediately after RPO etching to form contact openings. Thus the original photoresist mask is still on the RPO. In the second approach, the photoresist mask is re-formed prior to PAI to protect the RPO from implant damage.

Method for performing a pre-amorphization implant (PAI) which provides reduced resist protect oxide damage and reduced junction leakage

A method is disclosed for increasing the capacitance of high-density DRAM devices by microlithographic patterning. A semiconductor substrate having a MOS transistor comprising a gate and source/drain regions, and a word line and a bit line is provided. A layer of inter-poly oxide is deposited over the substrate and planarized. Contact holes are etched in the oxide layer until the substrate is exposed. A layer of photoresist is next blanket deposited over the substrate. Using microlithographic methods, the photoresist is then patterned with in-line or staggered micron size features and the underlying inter-poly oxide layer is etched using the photoresist as a mask. The resulting inter-poly oxide surface, therefore, acquires the shape of a micro-folded topography having a roughened surface area of many folds larger than the original flat surface. A first conductive layer such as polysilicon is conformally deposited over the microlithoqraphically roughened surface forming the storage electrode of the capacitor which is completed by forming a high dielectric oxide such as ONO over the first polysilicon and then depositing a second polysilicon to form the upper electrode of the capacitor.

Increasing capacitance for high density DRAM by microlithography

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Taichung, Taiwan

Ding-Dar Hu