Applied Materials, Inc.

Dinesh Saigal

Arvind Sundarrajan

Xianmin Tang

Peijun Ding

Anantha K Subramani

Muhammad M Rasheed

Rongjun Wang

Mingwei Zhu

Cheng-Hsiung Matt Tsai

Omkaram Nalamasu

Vivek Agrawal

Praburam Gopal Raja

Nag B Patibandla

Kenny King-Tai Ngan

Shankarram Athreya

Lisa L Yang

James Van Gogh

Nag B Patibandia

Shuk Ying Lai

Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.

PVD buffer layers for LED fabrication

Embodiments of the present invention generally relate to processes of making an improved salicide-gate. One embodiment of a method for forming a feature on a substrate comprises forming a gate structure on a substrate; forming spacers by the sidewalls of the gate; and depositing a relatively thin metal film, such as cobalt or titanium, over the gate at a high temperature.

Method for high temperature metal deposition for reducing lateral silicidation

A physical vapor deposition apparatus is provided with at least one workpiece processing chamber and a programmable control device for controlling process variables within the processing chamber. The control device is programmed to vary the power to an aluminum sputtering target during deposition of aluminum layers. By controlling the applied power, the rate of deposition of the aluminum is varied in a manner which reduces or avoids the creation of voids during the filling of high aspect ratio features.

Physical vapor deposition apparatus with deposition and DC target power control

A method of forming solder bumps on a semiconductor wafer utilizing a low temperature biasable electrostatic chuck. In particular, the method comprises the steps of providing at least one bond pad on the semiconductor wafer, forming a barrier layer over the bond pad, and forming the solder bumps upon the at least one bond pad. By controlling the temperature and biasing of the electrostatic chuck, the barrier layer, such as nickel vanadium, exhibits a low tensile or compressive stress.

Method of forming solder bumps on a semiconductor wafer

A method and apparatus for baking-out and for cooling a vacuum chamber are provided. In a first aspect, an inert gas which conducts heat from the vacuum chamber's bake-out lamps to the shield and from the shield to the other parts within the vacuum chamber is introduced to the chamber during chamber bake-out. The inert gas preferably comprises argon, helium or nitrogen and preferably raises the chamber pressure to about 500 Torr during chamber bake-out. A semiconductor processing apparatus also is provided having a controller programmed to perform the inventive bake-out method. In a second aspect, a process chamber is provided having at least one source of a cooling gas. The cooling gas is input to the chamber and is allowed to thermally communicate with the chamber body and components. The cooling gas may reside in the chamber for a period of time or may be continuously flowed through the chamber. Once the chamber reaches a target temperature the cooling gas is evacuated.

Method for improved chamber bake-out and cool-down

Methods for baking-out and for cooling a vacuum chamber are provided. In a first aspect, an inert gas which conducts heat from the vacuum chamber's bake-out lamps to the shield and from the shield to the other parts within the vacuum chamber is introduced to the chamber during chamber bake-out. The inert gas preferably comprises argon, helium or nitrogen and preferably raises the chamber pressure to about 500 Torr during chamber bake-out. A semiconductor processing apparatus also is provided having a controller programmed to perform the inventive bake-out method. In a second aspect, a process chamber is provided having at least one source of a cooling gas. The cooling gas is input to the chamber and is allowed to thermally communicate with the chamber body and components. The cooling gas may reside in the chamber for a period of time or may be continuously flowed through the chamber. Once the chamber reaches a target temperature the cooling gas is evacuated.

The present disclosure pertains to our discovery that a specialized set of process variables will enable the performance of second layer aluminum metallization of multi-layered semiconductor structures within a single processing chamber, without the need for deposition of a nucleation layer of aluminum, and without the need for a reflow step to fill voids formed during metallization. In general, the improved method of the invention includes the following steps: (a) sputter etching the patterned dielectric surface; (b) depositing at least one continuous wetting layer of titanium over the patterned dielectric surface using ion sputter deposition, the wetting layer having a thickness within the range of about 25 &angst; to about 200 &angst; on the sidewall of a contact via formed in the substrate; and (c) depositing a layer of aluminum over the titanium wetting layer using traditional sputter deposition at a substrate temperature within the range of about 380&deg; C. to about 500&deg; C. The substrate temperature is held substantially constant during deposition of the aluminum layer. The deposition rate of the aluminum layer is increased as the deposition progresses, preferably by increasing the target power as the deposition progresses. The method of the invention is particularly useful for second layer metallization of contact vias having aspect ratios up to about 4:1.

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San Jose, CA, United States of America

Dinesh Saigal