Cypress Semiconductor Corporation

Dinesh Nadavi

Brenor L Brophy

Xiao Ming Xi

Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits are populated upon a printed circuit board to control those integrated circuits using a standard JTAG interface, well-known as the IEEE Std. 1149.1 interface. A shift register used to control one or more electronic subcomponents can be programmed, written to, or read from using JTAG programming languages. However, the shift register, or multiple shift registers, used to control electronic subcomponents need not be JTAG compliant. The shift registers may be those found within proprietary circuits, such as analog-to-digital converters or digital-to-analog converters, and include any shift register than receives serial data and produces parallel data, or vice-versa, where the loading and serial shifting of data is controlled using a generic interface, such as enable, reset, capture, etc. One or more shift registers can be distributed among one or more integrated circuits proprietary to the manufacturer of that circuit, and the circuits which embody the shift registers need not have a JTAG interface. Yet, the shift registers can be controlled by a single test access port (TAP) external to the integrated circuits, but which controls the non-JTAG compliant shift registers of each integrated circuit bearing the same. This allows a JTAG programming language which can be readily obtained off-the-shelf to control integrated circuits which do not recognize JTAG control signals, nor do such integrated circuits necessarily have a JTAG four-pin interface.

Architecture, circuitry and method for controlling a subsystem through a JTAG access port

A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure. Instructions which begin and end the test operation are forwarded from a test device that is linked to the test system by a JTAG access port configured according to IEEE Std. 1149.1. This allows non-proprietary instructions to be sent into the access port controller, using only a single input pin among the four-pin JTAG access port, where a decoder within the test system is programmed to decode that instruction and either begin or end the test operation. A clock generation circuit will generate a high speed clock, for use by the physical device, to allow the physical device to operate at speed without requiring a costly test system to generate a high-speed clock and signals proprietary to that test system.

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Cupertino, CA, United States of America

Dinesh Nadavi