Texas Instruments Corporation

Analog Devices,inc.

Dinesh Jain

Srikanth Manian

Srinivas Theertham

Jagdish Chand

Markus Dietl

Kaushal Kumar Jha

A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input.

Low power comparator

A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a &#x3a3;&#x394; modulator and a summer to utilize an input N.&#x3b1; control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or &#x3b2; value of the full quadrant analog interpolator.

Fractional clock generator

In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

Synchronous clock generation using an interpolator

A voltage-to-current converter includes an input stage having a first input and a second input. The first input is connectable to a reference voltage, wherein the voltage of the second input is substantially the same as the voltage at the first input. A feedback loop is coupled between the second input and a voltage feedback node. A current feedback node is connectable to a first node of a resistor; the second node of the resistor is connectable to a voltage input, wherein a bias voltage of the current feedback node is set by the voltage of the voltage feedback node. At least one current mirror mirrors the current input to the current feedback node, the output of the at least one current mirror is the output of the voltage-to-current converter.

Voltage-to-current converter

Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.

Fixed frequency divider circuit

An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.

Analog to digital converter

An asynchronous analog-to-digital converter (AADC) and a method of using the AADC are shown. The AADC includes a digital-to analog-converter (DAC), a continuous-time comparator that provides an output including a digital value of the DAC and a time value, and a first and a second continuous-time summer, each connected to receive an analog differential input on a first input, to receive a differential output of the DAC on a second input, and to provide a difference between the analog input and the output of the DAC to the continuous-time comparator and to an error estimator. The continuous-time comparator provides the output responsive to the difference between the analog input and the output of the DAC being zero.

Asynchronous analog-to-digital converter

A system and method for calibrating an RDAC to obtain an expected resistance are disclosed. In one embodiment, a method of obtaining an expected resistance from an RDAC circuit includes receiving a digital signal comprising a digital code by an on-chip calibration code engine, automatically deriving a calibrated digital code based on resistance versus digital code characteristic curves of an expected RDAC and the RDAC associated with the calibration code engine, and inputting the calibrated digital code into the RDAC associated with the calibration code engine to obtain an expected resistance. The method also includes forming the resistance versus digital code characteristic curves of the expected RDAC and the RDAC, computing a gain error and an offset error using the formed resistance versus digital code characteristic curves of the RDAC and the expected RDAC and storing the gain error and the offset error in a non-volatile/volatile RDAC memory.

Method and apparatus for calibrating an RDAC for end-to-end tolerance correction of output resistance

A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 2LSB (least significant bit) voltage levels are generated as outputs from 2cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n&#x2212;2) bits and (2n&#x2212;1) bit resolution with lower SNDR are achieved by using 2resistors and two current sources. In one described embodiment, 2unit impedances in the cyclic string result in 2(n&#x2212;1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.

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Bengaluru, India

Dinesh Jain