Rambus Inc.

Altera Corporation

Intel Corporation

Meta Platforms Technologies, LLC

Facebook Technologies, LLC

Dinesh D Patil

Amir Amirkhany

Frederick Abbott Ware

Kambiz Kaviani

Mohammad Hekmat

Suresh Rajan

Jeffrey Erik Schulz

Neeraj Upasani

Farrukh Aquil

David Wolk Mendel

Sudhir K Satpathy

Keith Duwel

Gary Brian Wallichs

Wojciech Stefan Powiertowski

Jakob Raymond Jones

Arifur Rahman

Dana How

Reza Navid

Chuan Thim Khor

Shrirang Madhav Yardi

Wai Tat Wong

Kok Hong Chan

Brian S Leibowitz

Tim Tri Hoang

Jihong Ren

Yanjing Ke

Minqing Cai

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Semiconductor memory systems with on-die data buffering

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Optimizing power in a memory device

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Interface bridge between integrated circuit die

A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.

Distributed phased SRAM repair for systems on a chip

This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.

System on a chip (SOC) communications to prevent direct memory access (DMA) attacks

Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.

Artificial reality system with multi-stage boot process

The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.

Inline encryption of packet data in a wireless communication system

In an example of the described techniques, a wireless communication system includes first memory, second memory, a first microcontroller, and a second microcontroller. The first microcontroller manages drivers for a wireless transceiver and direct data movement between the wireless transceiver and the first memory. The second microcontroller communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory. Additionally, the second microcontroller direct data movement between the second memory and the first memory.

Wireless communication with code separation

System on a chip (SoC) communications to prevent direct memory access (DMA) attacks

Receiver circuitries having multiple branches, such as unrolled feedback equalizers and fractional-rate receivers, may present differences between filtering elements of different branches with common filter inputs. Embodiments include devices capable of calibration that compensates such differences. The devices may be capable of introducing front-end offsets to emphasize the mismatches, and sweep filter input values to calculate the mismatches, and introducing offsets in the branches to compensate for the mismatches. Methods for use of the calibration devices are also described.

Calibration for mismatch in receiver circuitry with multiple samplers

Growing community of inventors

Sunnyvale, CA, United States of America

Dinesh D Patil