Xilinx, Inc.

Dinesh D Gaitonde

Henri Fraisse

Ian A Swarbrick

Chirag Ravishankar

Sagheer Ahmad

Ygal Arbel

Amit Gupta

Salil Ravindra Raje

Yau-Tsun Steven Li

Aashish Tripathi

Maithilee Rajendra Kulkarni

Abhishek Kumar Jain

Steven P Young

Srinivas T Reddy

Trevor J Bauer

Brian C Gaide

Matthew H Klein

Sankaranarayanan Srinivasan

Grigor S Gasparyan

Pradip Jha

Xiaojian Yang

Ramakrishna Kishore Tanikella

Frederic Revenu

Robert M Ondris

Vishal Suthar

Steven Li

Jinny Singh

Ashit Debnath

Himanshu Verma

Sachin K Bhutada

Ritesh Mani

A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

3D stacked device having improved data flow

Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

Software defined device variants

A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

Random reads using multi-port memory and on-chip memory blocks

Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

Time-division multiplexing (TDM) in integrated circuits for routability and runtime enhancement

A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs

An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Configurable network-on-chip for a programmable device

Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.

Dynamic scan chain and method

A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

Resolving timing violations in multi-die circuit designs

Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.

Routing circuit designs for implementation using a programmable network on chip

Method and system relate generally to generating a physical design for a circuit design. In such a method, a logical network is obtained from a logical netlist for the circuit design. A physical network for an integrated circuit chip is obtained. The physical network is converted into a routing graph. The logical network and the routing graph are combined to build an extended network. Routing is performed on the extended network for the logical netlist to perform placement and the routing concurrently to provide the physical design.

Performing placement and routing concurrently

Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

Placement, routing, and deadlock removal for network-on-chip using integer linear programming

A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.

Placing and routing an interface portion and a main portion of a circuit design

Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

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Fremont, CA, United States of America

Dinesh D Gaitonde