Freescale Semiconductor,inc.

Dina H Triyoso

Olubunmi O Adetutu

Voon-Yew Thean

James Kenyon Schaeffer, Iii

Bich-Yen Nguyen

Philip J Tobin

Tab Allen Stephens

Gregory S Spencer

Victor H Vartanian

Hsing H Tseng

Marc A Rossow

Darrell Roan

Rama I Hegde

Thuy B Dao

Kurt H Junker

David Gilmer

Scott Daniel Hector

Alexander A Demkov

Ross Edward Noble

Tien-Ying Luo

Randy W Cotton

A semiconductor process and apparatus includes forming first and second gate electrodes () by forming the first gate electrode () over a first high-k gate dielectric () and forming the second gate electrode () over at least a second high-k gate dielectric () different from the first gate dielectric (). Either or both of the high-k gate dielectric layers () may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g.,). As deposited, the initial layer () has an exposed surface () and an initial predetermined crystalline structure. An exposed thin surface layer () of the initial layer () is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.

Reverse ALD

A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Method for forming a through silicon via (TSV)

A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.

Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

A semiconductor device is provided which comprises a semiconductor layer (), a dielectric layer (), first and second gate electrodes () having first and second respective work functions associated therewith, and a layer of hafnium oxide () disposed between said dielectric layer and said first and second gate electrodes.

Semiconductor device with selectively modulated gate work function

A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N/D), helium, argon or a combination of any two or more of these. Additional anneals using ultraviolet radiation may be performed. These additional anneals may occur in non-oxidizing or oxidizing ambients.

Method of removing defects from a dielectric material in a semiconductor

A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl, purging the chamber with an inert, pulsing the chamber with an HO or DO, and purging the chamber with an inert.

In-situ nitridation of high-k dielectrics

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer () over a gate dielectric layer (), forming a transition layer () over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer () over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (). By forming the transition layer () with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer () is constructed having a lower region (e.g.,) with a polycrystalline structure and an upper region (e.g.,) with an amorphous structure that blocks silicon diffusion.

ALD gate electrode

A CMOS device is provided which comprises (a) a substrate (); (b) a gate dielectric layer () disposed on the substrate, the gate dielectric comprising a metal oxide; (c) an NMOS electrode () disposed on a first region of said gate dielectric; and (d) a PMOS electrode () disposed on a second region of said gate dielectric, the PMOS electrode comprising a conductive metal oxide; wherein the surface of said second region of said gate dielectric comprises a material selected from the group consisting of metal oxynitrides and metal silicon-oxynitrides.

Gate dielectric and metal gate integration

A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.

Semiconductor transistor having structural elements of differing materials

A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.

Method for treating a semiconductor surface to form a metal-containing layer

A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO)(ZrO), wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.

Electronic device including dielectric layer, and a process for forming the electronic device

A method for forming a semiconductor device () creates a dielectric layer () with high dielectric constant. An interfacial layer () is formed over a semiconductor substrate (). A dielectric layer () is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions () within the semiconductor substrate.

Method of forming a semiconductor device having a dielectric layer with high dielectric constant

A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

Growing community of inventors

Austin, TX, United States of America

Dina H Triyoso