Advanced Micro Devices Corporation

Cisco Technology, Inc.

Other

Din-I Tsai

Robert Alan Williams

Ching Yu

Jeffrey Roy Dwork

Jerry Chun-Jen Kuo

Pierre F Haubursin

John Mingyung Chiang

Jerry Weiming Kuo

Jing Li

Joji Thomas Mekkattuparamban

Ming Chi Chen

David Gary Roberts

Jiu An

Cheng-Jia Lai

Ramkrishna Vepa

Murtaza Chiba

Glen William Gibson

Henry Yeh

David Balmforth

Techniques are provided herein to add multicast media streams to teleconferencing sessions without the unwanted side effects that occur when a speaker's own media is echoed back to the speaker. Multicast and unicast media streams are generated by a network device, e.g., a conference bridge, and distributed to any number of endpoints, e.g., conference endpoints. A media selector is provided that selects the appropriate multicast or unicast media stream for forwarding to an associated network endpoint.

Switchable conference multicast streaming with dynamic asymmetry

Method and apparatus for generating and receiving an extended Vendor Specific Attribute (VSA) is disclosed. In one aspect, a extended format VSA may be generated containing at least a Vendor-Type field having a predetermined value and a Extended Vendor-Type field. A Vendor Specific Attribute packet generated and received in accordance with the teachings of this disclosure may have a field sequence of &#x3c;Type&#x3e; &#x3c;Length&#x3e; &#x3c;Vendor-ID&#x3e; &#x3c;Vendor-Type&#x3e; &#x3c;Length&#x3e; &#x3c;Vendor-Extended-Type&#x3e; &#x3c;Value&#x3e;, and may field lengths of Type=8 bits; Length=8 bits; Vendor-ID=32 bits; Vendor-Type 8 bits; Length=8 bits; Vendor-Extended-Type=32 bits; and Value=1 or more bytes.

32-bit vendor-extended-type vendor specific attribute

A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Power management indication mechanism for supporting power saving mode in computer system

A system for freezing a communication device in a debug mode has a clock control circuit arranged to produce an internal clock signal in response to an external clock signal. When a stop signal is asserted, the internal clock signal is fixed in its off state. As a result, operations of internal registers supplied with the internal clock signal freeze in a chosen state. A scan test may be performed to examine the internal registers in the chosen state. A bypass clock signal is supplied to control the internal clock signal so as to move the internal registers from one state to another. Thus, an event that causes an error may be recreated.

Freezing mechanism for debugging

A system for automatically resetting an interrupt output is provided in a network controller having an interrupt management block that asserts the interrupt output in response to interrupt events. The interrupt output may be asserted in a real time mode or in a batch mode. An interrupt register contains bits that represent various interrupt events. An interrupt control register has enable bits for enabling or disabling an interrupt in response to certain interrupt events represented in the interrupt register. Also, the interrupt control register contains an interrupt pin enable bit for enabling or disabling the interrupt output of the controller. In response to an interrupt enable command from a CPU, the interrupt pin enable bit is set to 1 to enable the activation of the interrupt output of the controller. In response to the activation of the interrupt output, the CPU performs read access to the interrupt register to read an interrupt event that caused the interrupt. When a read access to the interrupt register is detected, the interrupt pin enable bit in the interrupt control register is automatically reset to reset the interrupt output and prevent an internal interrupt request signal from activating the interrupt output.

Automatic disabling of interrupts upon entry into interrupt service routine

A data storage device has a control block at a first location for storing control data generated by a host system to provide control information to a peripheral device. This control block includes a first predetermined location for storing predetermined data that is generated by the host system. The data storage device also includes a status block at a second location for storing the status data generated by the peripheral device to provide status information to the host system. In addition, the status block includes a second predetermined location for storing the predetermined data. The first location of the control block and the second location of the status block are separate and independent. The peripheral device reads the predetermined data from the control block to write the predetermined data into the second predetermined location within the status block. The host system then reads the predetermined data from the second predetermined location of the status block.

Dedication of space in descriptor for minimizing data processing during communications between a peripheral device and a host system

A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Software read and write tracing using hardware elements

A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the network peripheral to operate in one of a plurality of modes. The reception indicator of the present invention asserts an interrupt signal at a respective optimum interrupt time for each of the modes. If the network peripheral is operating in a programmed I/O mode (i.e. a slave mode), a slave optimum interrupt time is determined. In this mode, a host processor unit within the host system reads portions of information packets from a readable data port in a host system interface. In this mode, an interrupt is asserted at the slave optimum interrupt time before a last byte of an information packet is expected to be received from the communications network. If the network peripheral is operating in a DMA (Direct Memory Access) mode, a DMA (Direct Memory Access) optimum interrupt time is determined. In this mode, the network peripheral automatically transfers the received information packet to a host memory of the host system. In this mode, an interrupt signal is asserted at the DMA optimum interrupt time before a last byte of an information packet is expected to be copied to the host memory. In this manner, the present invention allows the network peripheral and the host system to operate in one of the modes that is most efficient for data processing while at the same time issuing an interrupt at a respective optimum interrupt time for each of the modes.

Information packet reception indicator for reducing the utilization of a

An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a particular interrupt. An interrupt register from a plurality of interrupt registers is selected via an address decoder, and data bits from the selected interrupt register are steered to a data bus. Each interrupt register has a corresponding trailing edge detector which clears the data content of the interrupt register after a first one of a plurality of data processors has read the data bits of that interrupt register on the data bus to service that particular interrupt. In this manner, a second one of the data processors which also attempts to service that particular interrupt reads the cleared content of that interrupt register. Upon reading the cleared content of that interrupt register, the second one of the data processors is alerted to return to a foreground task since that particular interrupt has already been serviced. The present invention also provides an option for not clearing an interrupt register. In addition, the present invention may include a mechanism for processing interrupt information data bit portions at a time by data type within an interrupt register.

Mechanism for synchronizing service of interrupts by a plurality of data

Th present invention coordinates access to a shared resource, comprised of a plurality of segments, between a first device and a second device using an index and count mechanism. The present invention includes a respective descriptor, for each of the plurality of segments. Entries to the respective descriptors of the segments are maintained by the first device to inform the second device of activity between the first device and the shared resource. The present invention also includes a descriptor queue register, coupled to the first device and the second device. The first device writes an index into the descriptor queue register for indicating a starting descriptor of a corresponding segment that is available to the second device for access. The first device also writes a count into the descriptor queue register for indicating a subsequent number of descriptors, from the starting descriptor, of any corresponding segments that are available to the second device for access. By thus using this index and count mechanism, the second device does not poll the descriptors to determine any available segments within the shared resource thereby substantially eliminating bandwidth, delay, and data processing overhead associated with the polling process of the prior art. The present invention can be used to particular advantage when the first device is a CPU of a computer host system having a shared memory which is the shared resource and when the second device is a computer network peripheral device that couples the computer host system to a network of computers.

Using an index and count mechanism to coordinate access to a shared

A computer network peripheral device transfers received data packets to a storage unit of a host computer system on a nonsequential data packet portion by portion basis instead of a sequential whole data packet by whole data packet basis of the prior art. Any received data packet is segmented into a plurality of data packet portions, and the data packet portions may be transferred in a nonsequential order. Such nonsequential transfer of data packet portions to the storage unit of the host computer system may optimize efficient data processing of the data packets by the host computer system.

System for non-sequential transfer of data packet portions with

A data transfer method with peripheral precharge wherein a starting portion of an output data block targeted for a peripheral is transferred to an output buffer for the peripheral using programmed I/O or slave cycles and wherein a virtual address of the output data block is translated into a physical address while the peripheral begins transferring the starting portion from the output buffer and over an output path. A direct memory access operation by the peripheral transfers a remainder portion of the output data block into the output buffer.

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Fremont, CA, United States of America

Din-I Tsai