Cypress Semiconductor Corporation

Cirrus Logic Inc.

Freescale Semiconductor,inc.

Dimitris Pantelakis

Anup Nayak

Robert Arthur Jensen

S Babar Raza

Walter Francis Bridgewater, Jr

Vikram Shenoy

John L Melanson

Mark A Ross

Derwin W Mattos

Hamed Ghassemi

Wai Tong Lau

Fariborz Golshani

Mail Khoi

A clock detection and selection circuit () can include a first counter (-) that generates a first count value CNTaccording to a first clock signal CLKand a second counter (-) that generates a second count value CNTaccording to a second clock signal CLK. First separation-detect logic (-) and second separation-detect logic (-) determine if a pre-specified difference exists between a first count value (CNT/CNT') and second count value (CNT/CNT&#x2032;). According to such determinations, separation information (INFand INF) can be generated indicating which clock signal (CLKor CLK) is faster. Selection logic () can select a faster of the clock signals (CLKor CLK) if the separation information values confirm one another.

Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals

An arbiter circuit () can include a latch () that latches competing input signals (Req_A and Req_B) to generate latch output signals (latnand latn). A filter section () can prevent metastable states of latch output signals (latnand latn) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit () can activate a feedback signal (fb) after a predetermined delay (&#x3b4;), provided both output signals (Sel_A and Sel_B) remain inactive.

Asynchronous arbiter with bounded resolution time and predictable output state

A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.

System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock

Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Glitch-free memory address decoding circuits and methods and memory subsystems using the same

A memory circuit includes a memory structure having sets of redundant columns where each set of redundant columns can replace a column of the memory array that may include a defective cell. Selection of the redundant columns for a memory access is accomplished by performing an address comparison between the address provided to the memory and one or more predetermined values that indicate which portion of the data array each set of redundant columns replaces. Based on this address comparison, a column redundancy select signal is asserted when a set of redundant columns is selected. For a read operation, the column redundancy select signal propagates through redundant column logic select the appropriate data from a particular set of redundant columns. This redundant data that is selected is substituted for data stored in the memory array for the read operation. A de-select feedback signal is generated based on the column redundancy select signal The de-select feedback signal is self resetting by causing the column redundancy select signal to be de-asserted after a time period adequate for the memory operation to complete.

Self resetting high speed redundancy circuit and method thereof

An apparatus and method for processing a data input signal with a single ended sense amplifier. The single ended sense amplifier includes a transmission gate circuit and a control circuit coupled between a feedback inverter circuit and an output signal that is fed back to the feedback inverter circuit. An inverter circuit is coupled between an enable signal and the transmission gate and control circuits. During pre-charge operation, the input to the feedback inverter circuit is driven to a first state. The feedback inverter correspondingly drives the input signal to a sensing inverter to a state that is complementary to the input to the feedback inverter circuit, thereby assisting the pre-charge mode and substantially reducing time delay due to the input signal contending with the feedback inverter circuit. One advantage of the present invention is that sense amplifiers can be sized for faster sensing than would other-wise be feasible due to the excessive contention during the pre-charge mode.

High speed single ended sense amplifier

A stress test circuit and method for static random access memory (&ldquo;SRAM&rdquo;) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.

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Austin, TX, United States of America

Dimitris Pantelakis