Motorola Corporation

Dimitris C Pantelakis

Wai Tong Lau

William L Martino, Jr

John W Eagan

Frank Arlen Miller

Eric S Powers

Derrick Leach

An integrated circuit (,) includes an input buffer circuit (,) having an input stage (,), a delay element (,), inverter (,), and a level shifter (,). The input stage (,) receives an input signal and a first power supply voltage. The level shifter (,) has a pair of cross-coupled P-channel transistors (,and,) coupled to a second power supply voltage. The second power supply voltage is different than the first power supply voltage. The cross-coupled P-channel transistors (,and,) are coupled to first and second N-channel transistors (,and,). Each of the first and second N-channel transistors (,and,) and transistors (,) of the input stage (,) have relatively thick oxide layers. A gate of the first N-channel transistor (,) is coupled to the output of the input stage (,). A gate of the second N-channel transistor (,) is coupled to receive the input signal. The level shifter (,) provides a high speed level shifted output signal at the second power supply voltage level.

Integrated circuit having a high speed clock input buffer

An integrated circuit device includes low voltage internal circuitry and a first external pin which receives a first information signal. The first information signal provides operating information within a predetermined voltage range. The device includes a mode detector coupled to the first external pin. The mode detector provides a mode enable signal in response to the first information signal being at a voltage that is outside the predetermined voltage range. The device further includes a switchable regulator which provides a supply voltage to the low voltage internal circuitry to power the low voltage internal circuitry at a regulated voltage in a normal mode of the integrated circuit memory and at a higher voltage than the regulated voltage in response to the mode enable signal.

Circuit and method for enabling semiconductor device burn-in

A memory device (50) contains a first array of memory (12) and a second array of memory (14). The arrays (12 and 14) are coupled to four segmented current data buses (iGDLs) (16, 18, 20, and 22). When in a x36 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate directly with output buffers (56-59) through several current-to-voltage converters (24-31). When in a x18 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate through the converts (24-31), through a voltage bus (52 and 54, see also FIG. 3), to the output buffers (56-59). The change in wiring for x36 word mode versus x18 word mode is done either by a top-level metal option in fabrication or by user software programming whereby the device (50) is easily wired into one of two configurations while maintaining an advantageous speed/power product.

Memory data bus architecture and method of configuring multi-wide word

A sense amplifier (10) senses data by sensing a differential current signal comprised of a current (I.sub.1) flowing in an input terminal (12) and a current (I.sub.2) flowing in a complementary input terminal (22). During the sensing process, the sense amplifier (10) generates a first current flowing in a first FET (17) in accordance with the current (I.sub.1) flowing through the input terminal (12) and a second current flowing in a second FET (27) in accordance with the current (I.sub.2) flowing through the complementary input terminal (22). Two cross coupled inverters (16, 26) compare the first current (I.sub.1) with the second current (I.sub.2) and generate a differential output voltage signal, thereby sensing the data.

Circuit and process for sensing data

A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.

Growing community of inventors

Austin, TX, United States of America

Dimitris C Pantelakis