Arm Limited

Microsoft Technology Licensing, LLC

Dimitrios Kaseridis

Jamshed Jalal

Tushar P Ringe

Klas Magnus Bruce

Joseph Michael Pusdesris

Gurunath Ramagiri

Ashok Kumar Tummala

Mukund Ramakrishna

Michael Filippo

Paul Gilbert Meyer

Phanindra Kumar Mannava

Alex James Waugh

Mark David Werkheiser

Andrew John Turner

Ho-Seop Kim

Rania Hussein Hassan Mameesh

Rahul Srikumar

A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.

Apparatus and method for handling memory access requests

Providing multi-request arbitration grant policies for time-sensitive arbitration decisions in processor-based devices is disclosed. In this regard, a processor-based device provides an arbitration circuit that is configured to select a request tracker entry of a plurality of request tracker entries of a request tracker circuit to apply a multi-request arbitration grant policy. The arbitration circuit determines a count N of a plurality of requests associated with the request tracker entry, and determines a count R of resource elements that are available of a plurality of resource elements of an arbitrated resource. The arbitration circuit determines whether the count R of resource elements that are available is equal to or greater than N, and if so, issues a single arbitration grant for the plurality of requests associated with the request tracker entry to the request tracker circuit.

Providing multi-request arbitration grant policies for time-sensitive arbitration decisions in processor-based devices

The described technology provides a method including receiving a request for allocating an incoming cacheline to one of a plurality of SFT entries in a snoop filter (SFT), performing a tag lookup function for a tag of the incoming cacheline in the SFT, in response to determining that the incoming cacheline is not part of an existing sector of any of the plurality of SFT entries, finding one or more candidate SFT entries, wherein the candidate SFT entries can be converted to an aggregated entry, selecting one of the candidate SFT entries, and allocating the incoming cacheline to the selected SFT entry.

Cache coherence using dynamic coarse-grained tracking

The described technology provides a method including determining a cacheline sector associated with a snoop filter (SFT) having a plurality of SFT entries, determining a number of cachelines in the identified cacheline sector that are cached by one or more agents, and determining, based on the number of cachelines in the identified cacheline sector that are cached by one or more agents, a number of bits in a bit vector (BV) of one or more of the plurality of SFT entries, wherein the number of bits is required to track the one or more agents.

Cache coherence using adaptive coherency tracking based on cacheline size and cacheline sector size

Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

Methods and apparatus for transferring data within hierarchical cache circuitry

An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

Data processing network with flow compaction for streaming data transfer

A data processing system () incorporates a first exclusive cache memory () and a second exclusive cache memory (). A snoop filter () located together with the second exclusive cache memory on one side of the communication interface () serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry () serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

Cache retention data management

A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

I/O coherent request node for data processing network with improved handling of write operations

A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.

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Austin, TX, United States of America

Dimitrios Kaseridis