Applied Micro Circuits Corporation

Macom Connectivity Solutions, LLC

Dimitrios Giannakopoulos

Francesco Caggioni

Matthew D Brown

Ravi Subrahmanyan

Xingen James Ren

Glen Miller

Tracy Ma

Matthew Ornes

Ben Brown

Michael Hellmer

Jim Lew

Xingen (James) Ren

System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The 'out-of-frame' indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.

Power optimization mechanisms for framers by serializing frame alignment processes for multiple lanes

System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes 'out-of-frame' again, the framer can wake up from the inactive state and restart the frame alignment process. An 'out-of-frame' indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.

Power optimization mechanisms for framers by selectively deactivating frame alignment process

System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.

Power optimization mechanisms for framers by using serial comparison in frame alignment process

Various aspects provide for non-intrusively monitoring a network system. A multiplexing component is configured to receive a plurality of first encoded signals and generate a plurality of second encoded signals. The plurality of second encoded signals contain a different data rate and a different number of network lanes than the plurality of first encoded signals. A monitoring component is configured to identify a block location for repeating blocks and an alignment marker in each of the plurality of first encoded signals and/or the plurality of second encoded signals. The monitoring component can also be configured to identify one or more defects, identify error information and/or determine one or more skew values associated with the plurality of first encoded signals and/or the plurality of second encoded signals.

System and method for monitoring encoded signals in a network

Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.

Mapping a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals

Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component. In another aspect, the maintenance signal can replace the defective signal during de-aggregation

Defect propagation of multiple signals of various rates when mapped into a combined signal

Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.

Reformating a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals

Various aspects provide for modifying a data stream for rate adaptation. A clock component receives a data stream at a first clock rate. In an aspect, a rate adaptation component inserts a first identification codeword into a particular location in the data stream based on a set of encoding rules in response to a determination that the first clock rate is lower than a second clock rate associated with a device configured for receiving a rate-adapted version of the data stream. In another aspect, the rate adaptation component removes a predefined codeword from the data stream and transforms another predefined codeword in the data stream into a second identification codeword in response to a determination that the first clock rate is greater than the second clock rate.

Identification codewords for a rate-adapted version of a data stream

An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo 100GBASE-R logical lanes. Further, the pseudo 100GBASE-R logical lanes from each group are arranged into a 100G attachment logical lane. Finally, a 100G attachment logical lane is transmitted at an attachment interface on each of n physical lanes. In the reverse direction, each of n physical lanes accepts a 100G attachment logical lane at the attachment interface, and a de-aggregation process supplies a 10GBASE-R signal on each of ten client interface logical lanes.

System and method for the aggregation of 10GBASE-R signals into pseudo 100GBASE-R signals

A system and method are presented for providing packet and time division multiplex (TDM) services in a data communication interface. The method accepts packets at a first rate over a packet interface, and transfers time-sensitive data in the packets as packet data units (PDUs) having a smaller number of bits than a packet and a second rate, faster than the first rate. The method transforms the PDUs into frames in a first TDM protocol. Typically, the PDUs are transformed into units having a smaller number of bits than the PDU and a third rate, faster than the second rate. Then, the TDM frames are transmitted over a line interface.

System and method for packet and time division multiplexed transport

A system and method are provided for transporting a serial stream via a lower speed network using multiple parallel paths. At a transmitter, an optical or electromagnetic waveform is accepted representing a serial stream of digital information, and unbundled into n virtual information streams. Each virtual information stream is divided into a sequence of segments. Each segment is encapsulated, creating a sequence of packets by adding a start indicator to the beginning of each segment, and a terminate indicator to the end of each segment. Each packet is disinterleaved across m lanes and reinterleaved into n branches of framed data. Optical or electromagnetic waveforms representing the framed data are transmitted via n network branches. A receiver is also provided, which essentially reverses the above-described transmission method.

Ethernet to multilane optical transport network traffic interface

A system and method are provided for transporting Plesiochronous Digital Hierarchy (PDH) tributaries. The method accepts a plurality of PDH tributaries; generates a serial data stream of interleaved PDH tributaries; generates a serial control stream of signals for recovering the PDH tributaries; and, generates a clock signal for timing the data and control streams. The serial data stream of interleaved PDH tributaries is loaded into the payload of a data frame structure. Likewise, the serial control stream is loaded into the payload of a control frame structure. The data bytes of the serial data stream and the control bytes of the serial control stream are both transmitted at the same data rate. That is, there is a control byte generated for each data byte. Thus, the control bytes in the control frame structure are aligned with corresponding data bytes in the data frame structure.

Flexible tributary interface

Multiservice system and method for packet and time division multiplexed transport

A system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method provides information bytes at a nominal system clock-based data rate, which is about equal to a system clock, but may be adjusted. An external clock has a rate approximately equal to the system clock rate. The method generates SPEs with identically-positioned information bytes, regardless of differences between the system and external clock rates. The SPEs are combined with Transport Overhead (TOH) and transmitted as a message frame at the external clock rate. SPEs are generated maintaining the positions of the information bytes within each SPE, without pointer adjustments, despite differences between the system and external clock rates. Expressed another way, message frames are generated with payload and TOH sections, and the information bytes are located exclusively in the payload sections. As a result, constant pointer values (e.g., H/Hor V/V) are maintained for all the SPEs.

Growing community of inventors

Methuen, MA, United States of America

Dimitrios Giannakopoulos