Analog Devices,inc.

Dimitrios Efstathiou

Ken Gentile

A reconfigurable communication transmitter core includes a digital pulse-shaping filter to perform pulse-shaping operations upon a digital modulated signal and a finite state machine to controls operation and reconfiguration of the digital pulse-shaping filter. A first memory stores coefficients and a second memory stores data. A multiplier multiplies a data value stored in the second memory with a corresponding coefficient value stored in the first memory. An adder adds each multiplication product from the multiplier with the content of an accumulation register wherein the accumulation register accumulates the sum from the adder. A rounding unit rounds off the content of the accumulation register and to provide rounded-off content as an output of the reconfigurable communication transmitter core. The finite state machine reconfigures a look-up table value set in the first memory, the first memory having pre-stored therein pulse shaped filtered waveforms. The pulse shaped filtered waveform having been pre-calculated.

Digital reconfigurable core for multi-mode base-band transmitter

Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

Universal signal modulators

A digital radio tuner signal estimator receives a digitized in-phase (I) data signal and a digitized quadrature (Q) data signal and provides an estimated amplitude gain signal and an estimated signal-to-noise ratio signal value. The signal estimator includes a symmetrical matched I data digital filter having a first I filter section that filters the received I data signal and provides a first I data signal, and a second I filter section that filters the I data signal and provides a second I data signal. The signal estimator also includes a symmetrical matched Q data digital filter having a first Q filter section that filters the received Q data signal and provides a first Q data signal, and a second Q filter section that filters the Q data signal and provides a second Q data signal. The first and second I data signals and the first and second Q data signals are processed to compute an estimated amplitude gain. In addition, the first and second I data signals and the first and second Q data signals are processed to compute the estimated signal-to-noise ratio value. The present invention utilizes the symmetry of the FIR matched filter to facilitate providing signal estimation in a digital receiver.

Digital matched filtering for signal estimation in a digital receiver

A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal. The phase lock detector also compares the magnitude of the integrated phase error signal to the threshold signal value to determine if carrier phase lock has been achieved. Carrier frequency recovery occurs first and when the carrier frequency lock detector identifies carrier frequency lock, carrier phase recovery is then performed. Once the carrier phase lock detector identifies phase lock, then accurately received data is available for signal processing. The detector may be employed in either full digital demodulators (i.e., parameter estimation and correction are performed digitally) or hybrid demodulators (i.e., parameter estimation is performed digitally and carrier frequency and phase correction are performed in the continuous time domain).

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Greensboro, NC, United States of America

Dimitrios Efstathiou