Apple Inc.

Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

Dimitri Tan

Terence M Potter

Jeffrey T Brady

Christopher L Spencer

Michael J Schulte

Ralph Clay Taylor

William V Miller

Frank W Liljeros

Trinh Huy Nguyen

Carl E Lemonds

Mark D Earl

Jeffrey M Broton

Jeffrey P Rupley

In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.

Graphics processor cache for data from multiple memory spaces

In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

Hardware resource allocation system for allocating resources to threads

Techniques are disclosed relating to memory allocation in a graphics shader. In some embodiments, a memory for storing input data for operations by the shader is shared for multiple different types of tasks (e.g., pixel shading tasks and compute tasks). In some embodiments, a graphics device is configured to separately process different portions (e.g., tiles) of a frame of graphics data. In some embodiments, the graphics device is configured to dynamically adjust the number of frame portions processed in parallel based on allocation information, where the allocation information is determined based on requests for other types of tasks. This may prevent pixel shading tasks from stalling other tasks for extended periods and may allow dynamic adjustments memory allocation mid-render.

Memory allocation techniques for graphics shader

An example system includes a plurality of execution units, a shared resource, and an allocation control circuit. Each execution unit may generate a resource allocation request that includes a resource allocation size. The allocation control circuit may select a particular resource allocation request from the plurality of resource allocation requests, and determine an availability, based on an allocation register, of contiguous resource blocks within the shared resource. In response to determining that a number of the contiguous resource blocks satisfies a requested allocation size, the allocation control circuit may select an address corresponding to a particular resource block of the one or more contiguous resource blocks, and allocate the resource blocks to a corresponding execution unit. In response to a beginning of a second system clock cycle, the allocation control circuit may also update the allocation register based on the selected address and the requested allocation size.

Pipelined resource allocation using size aligned allocation

A central processing unit includes a register file having a plurality of read ports, a first execution unit having a first plurality of input ports, and logic operable to selectively couple different arrangements of the read ports to the input ports. A method for reading operands from a register file having a plurality of read ports by a first execution unit having a first plurality of input ports includes scheduling an instruction for execution by the first execution unit and selectively coupling a particular arrangement of the read ports to the input ports based on a type of the instruction.

Sharing register file read ports for multiple operand instructions

A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

Division with rectangular multiplier supporting multiple precisions and operand types

A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

Growing community of inventors

Austin, TX, United States of America

Dimitri Tan