Stmicroelectronics S.a.

Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (crolles 2) Sas

Dimitri Soussan

Sylvain Majcherczak

Philippe Roche

Marc Belleville

Fady Abouzeid

Gilles Gasiot

Alexandre Valentian

Martin Cochet

Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Device for measuring doses of ionizing particles

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.

Output stage formed inside and on top of an SOI-type substrate

Growing community of inventors

Grenoble, France

Dimitri Soussan