Everspin Technologies, Inc.

Globalfoundries Singapore Pte. Ltd.

Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Globalfoundries Inc.

Sandisk Technologies Inc.

Institut Polytechnique De Grenoble

Le Commissariat a L'energie Atomique Et Aux Energies Altenatives

Dimitri Houssameddine

Jon Michael Slaughter

Syed M Alam

Nicholas David Rizzo

Renu Whig

Jijun Sun

Frederick B Mancoff

Jason A Janesky

Thomas Andre

Chenchen Jacob Wang

Sanjeev Aggarwal

Taiebeh Tahmasebi

Ursula Ebels

Michael Nicolas Albert Tran

Bertrand Delaet

Mark F Deherrera

Bin Liu

Chitra K Subramanian

Frederick Charles Neumeyer

Sumio Ikegawa

Marie-Claire Cyrille

Han Kyu Lee

Cristian P Masgras

Iftekhar Rahman

Pedro Sanchez

Hamid Almasi

Michael Schneider

Eng Huat Toh

Ward M Parkinson

Kangho Lee

Bernard Dieny

Michael Grobis

Soh Yun Siah

Vinayak Bharat Naik

Chim Seng Seet

Ricardo Sousa

Kazutaka Yamane

Juan Pablo Saenz

Wen Siang Lew

Kai Hung Alex See

Wai Cheung Law

Seungmo Noh

Liliana Buda-Prejbeanu

Cristian Papusoi

Marie Claire Cyrille

Teck Leong Wee

Deniz Bozdag

Mark Lin

John Slaughter

The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Systems and methods for monitoring and managing memory devices

An apparatus is provided that includes a memory cell having a reversible resistance-switching memory element coupled in series with a selector element. The selector element has a first resistance. The resistance-switching memory element is configured to reversibly switch between a second resistance and a third resistance. The memory cell may be selectively configured as either a re-writeable memory cell or a one-time programmable memory cell. The memory cell functions as a one-time programmable memory cell regardless of whether the resistance-switching memory element has the second resistance, the third resistance, or is electrically shorted.

One-time programmable memory devices and methods

Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is successful. Therefore, most of the time the read is completed with just the first SRR, thereby providing for an SRR having on average is faster than if just the second SRR had been used. Moreover, the effective BER of the SRR is extremely low due to the low BER of the second SRR.

Fast self-referenced read of programmable resistance memory cells

The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

Systems and methods for configuration of a configuration bit with a value

A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Magnetoresistive stack and method of fabricating same

Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Short detection and inversion

Magnetic field assisted magnetoresistive random access memory (MRAM) structures, integrated circuits including MRAM structures, and methods for fabricating integrated circuits including MRAM structures are provided. An exemplary integrated circuit includes a magnetoresistive random access memory (MRAM) structure and a magnetic field assist structure to generate a selected net magnetic field on the MRAM structure.

Magnetic field assisted MRAM structures, integrated circuits, and methods for fabricating the same

Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The base layer includes a seed layer and a roughness suppression layer. The spin transfer torque magnetic random access memory structure further includes a hard layer over the base layer. Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the hard layer and a top electrode over the MTJ element.

Magnetic random access memory structures, integrated circuits, and methods for fabricating the same

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

Integrated circuits with magnetic tunnel junctions and methods of producing the same

Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode, a seed layer over the bottom electrode, a hard layer over the seed layer, a magnetically continuous transition layer over the hard layer, a reference layer over the magnetically continuous transition layer, a tunnel barrier layer over the reference layer, a storage layer formed over the tunnel barrier layer, and a top electrode. The reference layer, the tunnel barrier layer, and the storage layer form a magnetic tunnel junction (MTJ) element with a perpendicular orientation.

Growing community of inventors

Gilbert, AZ, United States of America

Dimitri Houssameddine