Massachusetts Institute of Technology

Amberwave Systems Corporation

Nanyang Technological University

Dimitri A Antoniadis

Eugene A Fitzgerald

Judy L Hoyt

Zhiyuan Cheng

Zhi-Yuan Cheng

Anthony J Lochtefeld

Matthew T Currie

Dale C Flanders

Henry Ignatius Smith

Michael W Geis

Chirn Chye Boon

Pilsoon Choi

An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

Apparatus and method for wireless communication

A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.

Method of forming a digitalized semiconductor structure

A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded SiGebuffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop SiGelayer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop SGelayer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed SiGelayer, strained SiGelayer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.

Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers

FinFET structure and method to make the same

In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

Gate material for semiconductor device fabrication

A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded SiGebuffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop SiGelayer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop SiGelayer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed SiGelayer, strained SGelayer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.

Semiconductor device structure

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded SiGe(x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed SiGelayer, a thin strained SiGelayer and another relaxed SiGelayer. Hydrogen ions are then introduced into the strained SiGelayer. The relaxed SiGelayer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed SiGelayer remains on the second substrate. In another exemplary embodiment, a graded SiGeis deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Process for producing semiconductor article using graded epitaxial growth

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si Ge (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si Ge layer, a thin strained Si Ge layer and another relaxed Si Ge layer. Hydrogen ions are then introduced into the strained Si Ge layer. The relaxed Si Ge layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si Ge layer remains on the second substrate. In another exemplary embodiment, a graded Si Ge is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Semiconductor substrate structure

Improvements on the graphoepitaxial process for obtaining epitaxial or preferred orientation films are described wherein a cap of material is formed over the film to be oriented, artificial surface-relief structure may be present in the substrate, the cap, or both, and the film may be heated by irradiation with electromagnetic radiation.

Growing community of inventors

Brookline, MA, United States of America

Dimitri A Antoniadis