Microsoft Technology Licensing, LLC

Western Digital Technologies, Inc.

S-tec Corporation

Stmicroelectronics Gmbh

Hgst Technologies Santa Ana, Inc.

Hgst Netherlands, B.v.

Dillip Kumar Dash

Benito Joseph Rodriguez

Bhasker R Jakka

Umang Thakkar

Levente Peter Jakab

Shu-Ming Chang

Po Chun Yang

Jake Bear

Juan-Yi Wu

Sivagnanam Parthasarathy

Xinde Hu

Majid Nemati Anaraki

Alessandro Risso

Lun Bin Huang

Aniryudh Reddy Durgam

Amir Alavi

Vamsi Sata

Haritha Uppalapati

James V Henson

Hadi Torabi Parizi

Namhoon Yoo

Rohit Komatineni

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.

Printed circuit board mesh routing to reduce solder ball joint failure during reflow

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil&#xd7;8 mil cuts or indentations in the copper shape.

Systems, methods, and software are disclosed herein that enhance data storage operations. In various implementations, a preserve write process identifies one or more regions of the solid-state memory components that qualify to be relocated prior to a data storage device entering a data retention state. Prior to the data retention state, the process changes one or more values, of one or more write settings, to one or more new values. With the write settings changed to the one or more new values, the process relocates data from the one or more regions to one or more new regions. After having relocated the data, the process returns the one or more new values, of the one or more write settings, to one or more earlier values.

Preserve write for solid-state drives

A method for managing a flash storage system includes measuring an operation time to complete a data operation on a flash memory block of a flash memory device of the flash storage system. The method includes updating, based on the measured operation time, a running average time for the flash memory device to complete the data operation. The method includes comparing the updated running average time to a threshold time. The method includes adjusting an operating parameter for the flash memory device to perform the data operation based on the comparison.

Continuous adaptive calibration for flash memory devices

The subject technology provides a decoding solution that conserves variable node memory in Low Density Parity Check decoding operations, while supporting multiple choices of code rates. A decoder includes a plurality of variable node memories, with each of the variable node memories having a predetermined memory capacity based on a position of a respective variable node associated with the variable node memory relative to a first variable node in a series of variable nodes. The code rate determines how many of the variable node memories are used, and the size of the data stored in each memory. The capacity of the memories is predetermined so that, as the code rate and number of memories utilized by the decoder increases or decreases, utilization of the memory capacity of each variable node memory is maximized.

Tapered variable node memory

An encoder that supports multiple code rates and code lengths is disclosed. A shift register utilized by the encoder may be scaled in size based on a selected code rate or code length. The shift register shifts a bit series for the matrix without requiring fixed feedback points within the register. The sizes of the matrix and bit series are based on the selected code rate or code length, and the encoder loads the bit series into a first portion of the shift register, and a division of the bit series into a second portion of the shift register located adjacent to the first portion. The encoder periodically repopulates the shift register from memory to simulate circular shifting of the bit series without feedback points. Accordingly, complexity of the encoder is reduced.

Encoder supporting multiple code rates and code lengths

In general, techniques are described for resource allocation and deallocation that facilitates power management. A device comprising one or more processors and a memory may be configured to perform the techniques. The processor may be configured to determine usage of a first non-zero subset of a plurality of resources, the plurality of resources allocated and released in accordance with a thermometer data structure. The processors may further be configured to compare the usage of the first non-zero subset of the plurality of resources to a threshold separating the first non-zero subset of the plurality of resources from a second non-zero subset of the plurality of resources, and power on the second non-zero subset of the plurality of resources based at least on the comparison. The memory may be configured to store the threshold.

Resource allocation and deallocation for power management in devices

A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller.

System and method for scanning flash memories

Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Power arbitration for storage devices

The subject technology provides a decoding solution that supports multiple choices of code rates. A decoder may be configured to receive a selected code rate from a plurality of code rates. On the selection of the code rate, the decoder may determine a circulant size based on the code rate, and, on receiving the codeword, update, during one or more parity-check operations, a number of confidence values proportional to the circulant size in each of a plurality of memory units, each number of confidence values corresponding to a portion of the codeword.

Low density parity check code decoding system and method

The subject disclosure describes a method for performing error code correction, the method includes, loading a code word including a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits includes soft information. In certain aspects, the method further includes decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided.

High speed hard LDPC decoder

A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.

Closely coupled vector sequencers for a read channel pipeline

A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit receives, from the plurality of encoders, respective requests for a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders at staggered times for use in respective encoding operations.

Reduced memory multi-channel parallel encoder system

A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based on that instruction. The instruction set further includes flow control instructions allowing for repetitive execution of a single instruction, repetitive execution of a block of instructions or branching within a program. Such a processor is illustrated in connection with a disk controller for a hard drive of a computer. The flexible sequencing allows a hard-drive controller to be readily reprogrammed for use in connection with different types of media or to be dynamically reprogrammed upon detection of a disk read error to increase the ability of the disk controller to recover data from a disk.

Growing community of inventors

San Diego, CA, United States of America

Dillip Kumar Dash