Advanced Micro Devices Corporation

Ati Technologies Ulc

Dilip Kumar Jha

Alexander J Branover

Benjamin Tsien

James Raymond Magro

William Louie Walker

Hui Zhou

Kostantinos Danny Christidis

Mom-Eng Ng

MingLiang Lin

Durgesh Kumar

A cache cleaner controller is described. In one or more examples, an apparatus includes a cache directory including status bits associated with cache locations within cache storage and a cache cleaner controller. The cache cleaner controller is configured to detect that a cache cleaner threshold has been reached. The cache cleaner threshold defines that a threshold number of the status bits indicate data maintained at the cache locations, respectively, has been changed. The cache cleaner controller is also configured to cause the data indicated as changed by the status bits to be copied from the cache locations within cache storage to the physical volatile memory.

Smart cache cleaner

A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.

Data fabric C-state management

A system and method for fast save/restore is disclosed. The system and method include one or more logical units (LUs) residing in independent power domains, one or more digital frequency synthesizers (DFS), each of the one or more DFS associated with one of the one or more LUs, the one or more DFSs configured to lock a system complex frequency and ramp the one or more LUs to system complex frequency, and one or more slave fast save/restore control (FSRC) units, each slave FSRC unit associated with one of the one or more LUs, the one or more slave FSRC units configured to save/restore the FSRC states of the one or more LUs.

System and method to reduce power down entry and exit latency

Growing community of inventors

Hyderabad Telangana, India

Dilip Kumar Jha