Qualcomm Incorporated

Dileep Marchya

Srinivas Pullakavi

Dhaval Kanubhai Patel

Balamukund Sripada

Mastan Manoj Kumar Amara Venkata

Nagamalleswararao Ganji

Sudeep Ravi Kottilingal

Gopikrishnaiah Andandan

Prashant Nukala

Mahesh Aia

Sushil Chauhan

Padmanabhan Komanduru V

Nan Zhang

Yongjun Xu

Kalyan Thota

Rajesh Yadav

Panneer Arumugam

Ujwal Patel

Mohammed Naseer Ahmed

Ramkumar Radhakrishnan

Saurabh Shah

Padmanabhan Komanduru, V

Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first frame, where the partial frame update for the first frame is associated with a panel ROI of the first frame. The apparatus may also calculate a margin time period between the first update time and a subsequent Vsync time. Further, the apparatus may transmit, based on the margin time period, a first indication of a subsequent frame transfer interrupt time. The apparatus may also transmit, to a DPU, a second indication to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting at the subsequent frame transfer interrupt time.

Display processing unit pixel rate based on display region of interest geometry

Aspects of the disclosure are directed to implementing adaptive variable refresh (AVR) wherein a graphics processing unit (GPU) is configured to generate a display content; a display processing unit (DPU) coupled to the graphics processing unit (GPU), wherein the DPU is configured to provide an adaptive variable refresh (AVR) feature; and a display panel coupled to the DPU, wherein the display panel is configured to display the display content.

Adaptive synchronization for fluid display refresh rate changes

The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate regional processing of images for under-display device displays. Aspects of the present disclosure can identify a subsection of a set of frame layers, the identified subsection corresponding to a lower pixel density region, relative to at least one other region, of a display. Aspects of the present disclosure can also blend first pixel data for each frame layer corresponding to the identified subsection to generate second pixel data. Further, aspects of the present disclosure can populate a buffer layer based on the second pixel data. Additionally, aspects of the present disclosure can blend pixel data from the set of frame layers and the buffer layers to generate a blended image. Aspects of the present disclosure can also transmit the blended image for presentment via the display.

Methods and apparatus to facilitate regional processing of images for under-display device displays

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Parallelization of GPU composition with DPU topology selection

The present disclosure relates to methods and apparatus for display processing. The apparatus can determine at least one data parameter corresponding to each of a plurality of layers in a display frame. The apparatus can also calculate a model for the at least one data parameter corresponding to each of the plurality of layers. Additionally, the apparatus can modify the model for the at least one data parameter based on one or more application use cases of the display frame. Moreover, the apparatus can implement the modified model on each of the plurality of layers in the display frame. In some aspects, the apparatus can also determine one or more composition settings for each of the plurality of layers based on the modified model. The apparatus can also apply the one or more composition settings to each of the plurality of layers based on the modified model.

Methods and apparatus for compositor learning models

In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Low latency composer

The present disclosure relates to methods and apparatus for display processing. Aspects of the present disclosure can determine a refresh offset for at least one group of lines in a first display based on at least one group of lines in a second display. Aspects of the present disclosure can also apply the refresh offset for the at least one group of lines in the first display based on the at least one group of lines in the second display. Further, aspects of the present disclosure can adjust combined instantaneous bandwidth corresponding to each of the at least one group of lines in the first display and each of the at least one group of lines in the second display based on the applied refresh offset. Aspects of the present disclosure can also determine one or more overlapping layer regions based on the first display and the second display.

Methods and apparatus for refreshing multiple displays

In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving, at a hardware voting component associated with a destination subsystem, metadata for each of a plurality of compressed display tiles, wherein for each of the plurality of compressed display tiles the metadata indicates an amount of compression of the compressed display tile. In some configurations, the method includes dividing the plurality of compressed display tiles into a plurality of sets of compressed display tiles. In some configurations, for each of the plurality of sets of compressed display tiles, the method includes determining a desired bandwidth for communicating the set of compressed display tiles over a bus, and receiving the set of compressed display tiles at the destination subsystem over the bus at an actual bandwidth that is based on the desired bandwidth.

Dynamic bandwidth voting

Techniques of this disclosure may include ways to control the amount of graphics data a graphics processing unit (GPU) renders. The GPU may render graphics data for image content that changed from frame-to-frame rather than graphics data for image content that changed and did not change. To display the image content, processing circuitry may map locations of where the graphics data is stored to lines in the image content allowing for the GPU to store the graphics data in arbitrary locations of an application buffer.

Arbitrary block rendering and display frame reconstruction

Certain aspects of the present disclosure provide a method for driving a plurality of display panels including a first display panel and a second display panel. The method includes receiving a first synchronization signal from the first display panel. The method further includes receiving a second synchronization signal from the second display panel. The method further includes determining a phase difference between the first synchronization signal and the second synchronization signal. The method further includes computing at least one phase shift offset based on the determined phase difference, the at least one phase shift offset being configured to reduce the phase difference between the first synchronization signal and the second synchronization signal. The method further includes providing a first phase shift offset of the at least one phase shift offset to the first display panel. The method further includes providing a unified synchronization signal to a display processor.

Systems and methods to synchronize display panels

A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, an example method may include causing a first region of a display to be refreshed without using a memory of the display, and causing a second region of the display to be refreshed using the memory of the display.

Content refresh on a display with hybrid refresh mode

Methods, systems, and devices for processing display data are described. A device may receive a bitstream sequence including a quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the device may be a decoding device or an encoding device. Upon receiving the bitstream sequence, the device may determine a refresh pixel region for a frame based on an order of the quantity of intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. In some examples, the order may be an encoding order of the intra-coded frames, inter-coded frames, or bi-directional frames, or a combination thereof. The device may then send the refresh pixel region for the frame to a display device based on determining the refresh pixel region for the frame.

Display refresh blocks determination for video coding

The present disclosure relates to methods and apparatus for video processing. Aspects of the present disclosure can identify one or more macroblocks (MBs) in a frame including a static luminance. In some aspects, the static luminance can be a luminance value that is static for a time period. Aspects of the present disclosure can also determine whether at least one MB of the one or more MBs includes the static luminance for a time period greater than or equal or a luminance threshold duration. Also, the present disclosure can adjust the luminance value of the at least one MB based on the determination whether the at least one MB includes the static luminance for a time period greater than or equal or the luminance threshold duration. Further, the present disclosure can store, as static luminance information, the determination whether the at least one MB includes the static luminance.

Methods and apparatus for improving image retention

A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.

Adaptive buffer latching to reduce display janks caused by variable buffer allocation time

The disclosure relates to a system including a set of subsystems sharing a voltage rail. The system includes a power controller configured to send messages, such as interrupts, to the subsystems concerning a change of state of a supply voltage on the voltage rail. Such messages may have been sent in response to requests and messages from the subsystems, respectively. In response to the messages, the subsystems may send requests to the power controller for different dynamic clock voltage scaling (DCVS) levels, respectively. In response to such requests, the power controller may set the supply voltage and frequencies of clock signals for the requesting subsystems, respectively.

Growing community of inventors

Hyderabad Telangana, India

Dileep Marchya