Samsung Electronics Co., Ltd.

Dikla Shapiro

Amit Berman

Ariel Doubchak

Evgeny Blaichman

Lital Cohen

Yaron Shany

Idan Dekel

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a frame corresponding to a codeword from the storage device, performing a first decoding operation on the frame, based on the first decoding operation indicating that a number of errors is greater than a predetermined number, selecting at least one potential error bit, and perform a second decoding operation based on the at least one potential error bit, based on the second decoding operation indicating that the number of errors is not equal to the predetermined number plus one, determining that the frame is not correctable by the first decoding operation and the second decoding operation, and based on the second decoding operation indicating that the number of errors is equal to the predetermined number plus one, correcting the frame based on a result of the second decoding operation to obtain a corrected frame, and obtaining information bits corresponding to the codeword based on the corrected frame.

High throughput polar codeword decoding by decoding bch sub-code in polar code structure

Systems, devices, and methods for decoding information bits obtained from storage, including obtaining a codeword from among a plurality of codewords stored in a storage device, wherein the codeword includes a plurality of frames; obtaining an initial error locator polynomial (ELP) corresponding to the codeword; decoding a frame of the plurality of frames; based on determining that the frame is successfully decoded, determine an updated ELP based on the initial ELP and information about the frame; and obtaining information bits corresponding to the codeword based on the updated ELP, wherein the updated ELP includes a plurality of updated coefficients, and wherein the updated ELP is determined by simultaneously calculating at least two updated coefficients from among the plurality of updated coefficients.

Fast polynomial division by monomial for Reed-Solomon ELP maintenance

A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Machine-learning error-correcting code controller

A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

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Ramat Gan, Israel

Dikla Shapiro