Texas Instruments Corporation

Diganta Baishya

Srinath Mathur Ramaswamy

Indu Prathapan

Sundarrajan Rangachari

Ranjit Kumar Dash

Sankar Prasad Debnath

Anjana Ghosh

An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Growing community of inventors

Bengaluru, India

Diganta Baishya